VHDL Code Examples: Unit Control HLSM and Button Press FSM
Unit Control HLSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UnitControl_HLSM is
port (clk, rst : in std_logic;
c : in std_logic;
A : in unsigned(7 downto 0);
z : out std_logic);
end UnitControl_HLSM;
architecture Behavior of UnitControl_HLSM is
begin
process(clk)
type UC_statetype is (UC_Init, UC_GetInput, UC_UnitOn);
variable UC_State : UC_statetype;
variable V : unsigned(7 downto 0);
begin
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