Digital Logic Circuits and Boolean Minimization Techniques

Posted on May 18, 2026 in Systems Computer Engineering

Binary Adders and Subtractors

A Half Adder is a combinational logic circuit that adds two single-bit binary numbers. It produces two outputs: Sum (S) and Carry (C). It is called a ‘half’ adder because it cannot handle a carry from previous additions.

Logic Expressions for Adders

  • Half Adder: Sum (S) = A XOR B; Carry (C) = A AND B (A·B)
  • Full Adder: This is a combinational circuit that adds three one-bit binary numbers: A, B, and Carry-in (Cin). It produces two outputs: Sum (S) and Carry-out (Cout). Full adders are used to build multi-bit adder circuits.
  • Full Adder Expressions: Sum = A XOR B XOR Cin; Carry = (A·B) + (B·Cin) + (A·Cin)

Binary Subtractors

A Half Subtractor performs subtraction of two single bits. It produces Difference (D) and Borrow (B) outputs. It cannot handle a borrow from a previous stage.

  • Half Subtractor Expressions: Difference (D) = A XOR B; Borrow (Bo) = A’·B (NOT A AND B)
  • Full Subtractor: This circuit subtracts three bits: Minuend (A), Subtrahend (B), and Borrow-in (Bin). Outputs are Difference and Borrow-out.
  • Full Subtractor Expressions: Difference = A XOR B XOR Bin; Borrow-out = A’·B + A’·Bin + B·Bin

Encoders and Decoders in Digital Systems

An Encoder is a combinational circuit that converts 2n input lines into n output lines. It encodes information by converting active input signals into a coded binary output. It performs the reverse operation of a decoder.

Common Encoder Types

  • Decimal to BCD Encoder (10 to 4 lines)
  • Octal to Binary Encoder (8 to 3 lines)
  • Hexadecimal to Binary Encoder (16 to 4 lines)
  • Priority Encoder

A Decoder is a combinational circuit that converts n binary input lines into 2n output lines. It activates exactly one output for each unique input combination, decoding the binary information.

Decoder Types and Applications

  • Types: 2-to-4 line Decoder, 3-to-8 line Decoder (Octal Decoder), 4-to-16 line Decoder, and BCD to Decimal Decoder.
  • Applications: Memory address decoding in computers, seven-segment display driving, instruction decoding in CPUs, and demultiplexing.

Boolean Simplification with Karnaugh Maps

A Karnaugh Map (K-map) is a graphical method for simplifying Boolean expressions. It was developed by Maurice Karnaugh in 1953. The K-map eliminates the need for algebraic manipulation and provides a systematic, visual method to obtain the minimized Sum of Products (SOP) or Product of Sums (POS) expressions.

Advantages and Procedure

  • Advantages: Reduces hardware, minimizes gates, and creates faster circuits.
  • Types: 2-variable, 3-variable, and 4-variable K-maps.
  • Procedure: Draw the K-map, fill in the values, group 1s in powers of 2, and obtain the simplified expression.

Don’t Care Conditions

Don’t Care Conditions are used when the output is irrelevant for certain inputs. They can be treated as 0 or 1—whichever provides better simplification. Include ‘don’t cares’ in groups only if it makes the group larger; they do not need to be covered otherwise. Using them can significantly reduce circuit complexity.

Characteristics of Digital Logic Families

A logic family is a collection of IC logic gates built using the same technology and sharing similar electrical characteristics. They are compatible in terms of supply voltage and input/output voltage levels.

Key Performance Parameters

  • Fan-out: Number of gates the output can drive without degradation.
  • Fan-in: Number of inputs a gate can handle.
  • Propagation Delay: Time for the output to respond after an input change.
  • Noise Margin: Tolerance against voltage fluctuations.
  • Power Dissipation: Power consumed per gate.
  • Speed-Power Product: Figure of merit calculated as delay × power.
  • Supply Voltage: VCC or VDD required to operate.

Bipolar and MOS Logic Families

  • RTL (Resistor Transistor Logic): Uses resistors and transistors. It features simple construction and low cost but suffers from slow speed, high power consumption, and low noise immunity.
  • DTL (Diode Transistor Logic): Uses diodes for logic and transistors for amplification. It offers better noise immunity and moderate fan-out compared to RTL but is slow due to charge storage.
  • TTL (Transistor Transistor Logic): The most widely used bipolar family. It uses multiple-emitter transistors, offering high speed and moderate power consumption.
  • CMOS (Complementary Metal Oxide Semiconductor): The dominant modern technology using PMOS and NMOS pairs. It features extremely low static power, high noise immunity, and low heat generation. Used in processors and mobile phones.
  • NMOS and PMOS: NMOS uses N-channel MOSFETs and is faster than PMOS. PMOS was the earliest MOS technology but is now largely replaced due to slow speeds.

Multiplexers and Demultiplexers

A Multiplexer (MUX) is a combinational circuit that selects one of many (2n) input lines and routes it to a single output line. It acts as a data selector controlled by n select lines, where the number of select lines = log2(Number of Inputs).

  • 4:1 MUX: 4 inputs, 2 select lines, 1 output
  • 8:1 MUX: 8 inputs, 3 select lines, 1 output
  • 16:1 MUX: 16 inputs, 4 select lines, 1 output

MUX and DEMUX Applications

  • MUX Applications: Data routing, implementing Boolean functions (universal logic element), parallel-to-serial conversion, and Time Division Multiplexing (TDM). IC 74153 is a dual 4:1 MUX; IC 74151 is an 8:1 MUX.
  • Demultiplexer (DEMUX): A circuit that takes one input and routes it to one of 2n output lines. It is the reverse of a multiplexer. A decoder with an enable pin can function as a DEMUX.
  • DEMUX Applications: Serial-to-parallel conversion, address demultiplexing, and TDM receivers.

The Quine-McCluskey Tabular Method

The Quine-McCluskey (QM) method, also called the Tabular Method, is a systematic, algorithmic method for minimizing Boolean functions. It is equivalent to the K-map but works for any number of variables and is suitable for computer implementation.

  • Steps: Write minterms in binary, group by the number of 1s, combine terms differing by one bit, find prime implicants, and select essential prime implicants.
  • Pros and Cons: It is suitable for automation and handles many variables, but it is lengthy to perform manually.

Sequential Logic and Flip-Flops

A flip-flop is a bistable multivibrator—a sequential logic circuit that can store one bit of information. It has two stable states (0 and 1) and changes state based on input signals and a clock. They are the building blocks of registers, counters, and memory.

Types of Flip-Flops

  • SR Flip-Flop: The simplest type with Set (S) and Reset (R) inputs. Characteristic equation: Q(next) = S + R’·Q, with the constraint SR = 0.
  • JK Flip-Flop: Eliminates the SR forbidden state. J (Set) and K (Reset) inputs allow a Toggle condition when JK=11.
  • D Flip-Flop: Has a single data input (D). It eliminates indeterminate states and stores one bit. Equation: Q(next) = D.
  • T Flip-Flop: Has a single Toggle input. If T=1, it toggles the state; if T=0, it holds the state. Equation: Q(next) = T XOR Q.

Applications of Flip-Flops

Flip-flops are essential for the construction of Registers, Counters, and various Memory systems.