Digital Electronics Principles, Logic Gates and Circuits

Posted on Oct 6, 2026 in Systems Computer Engineering

1. Universal Gates

NAND and NOR are universal gates because any logic function (AND, OR, NOT, etc.) can be built using only NAND gates or only NOR gates.

NAND-NOT:  A ─┬─[NAND]─ A'
              └─┘
NAND-AND:  A ─┐
              [NAND]─[NAND(tied)]─ AB
           B ─┘
NAND-OR:   A ─[NAND(tied)]─┐
                           [NAND]─ A+B
           B ─[NAND(tied)]─┘

2. Binary to Decimal

Multiply each bit by its positional weight (powers of 2) and add.

Example: (1101.101)₂ = 1×8 + 1×4 + 0×2 + 1×1 + 1×½ + 0×¼ + 1×⅛ = 8+4+0+1+0.5+0+0.125 = (13.625)₁₀

3. Decimal to Binary

• Integer part: divide repeatedly by 2 and read the remainders bottom to top.
• Fraction part: multiply repeatedly by 2 and read the integer parts top to bottom.

Example: (25.625)₁₀

25 ÷ 2 = 12 R 1        0.625 × 2 = 1.25 → 1
12 ÷ 2 =  6 R 0        0.25  × 2 = 0.5  → 0
 6 ÷ 2 =  3 R 0        0.5   × 2 = 1.0  → 1
 3 ÷ 2 =  1 R 1
 1 ÷ 2 =  0 R 1
→ 11001                → .101

(25.625)₁₀ = (11001.101)₂

4. 1’s and 2’s Complement

• 1’s complement: change every 0 to 1 and every 1 to 0.
• 2’s complement: 1’s complement + 1.

Example: N = 10110

• 1’s complement = 01001
• 2’s complement = 01001 + 1 = 01010

Use: subtraction A − B = A + (2’s complement of B). If a carry is generated, discard it and the result is positive. If there is no carry, the result is negative and appears in 2’s complement form.

5. Half Adder and Full Adder

Half adder adds two bits.

Sum = A ⊕ B, Carry = A·B

A ─┬────[XOR]─── Sum
B ─┼─┬──[XOR]
   │ │
   └─┴──[AND]─── Carry

Full adder adds three bits (A, B, Cin).

Sum = A ⊕ B ⊕ Cin, Cout = AB + Cin(A ⊕ B)

A ──┬──[HA1]── S1 ──[HA2]── Sum
B ──┘    └─C1─┐   └─C2─┐
Cin ─────────────┘     [OR]── Cout
                        (C1, C2)

A full adder is two half adders plus an OR gate.

6. Half Subtractor and Full Subtractor

Half subtractor computes A − B.

Diff = A ⊕ B, Borrow = A’·B

A ─┬────[XOR]─── Diff
B ─┼─┬──[XOR]
   │ └──────┐
   └─[NOT]──[AND]─── Borrow

Full subtractor computes A − B − Bin.

Diff = A ⊕ B ⊕ Bin, Bout = A’B + Bin(A ⊕ B)’

Built from two half subtractors and an OR gate (same layout as the full adder).

7. Multiplexer (MUX)

A multiplexer is a combinational circuit that selects one of many data inputs and sends it to a single output, based on the select lines. It has 2ⁿ inputs, n select lines and 1 output, and is also called a data selector.

4:1 MUX (S1, S0 select lines)

Y = S1’S0’·I0 + S1’S0·I1 + S1S0’·I2 + S1S0·I3

I0 ─[AND]─┐
I1 ─[AND]─┤
I2 ─[AND]─┼─[OR]── Y
I3 ─[AND]─┘
 (each AND gets a decoded S1, S0 combination)

Applications: data routing, parallel-to-serial conversion, implementing logic functions.

8. Flip-Flop with Truth Table

A flip-flop is a bistable circuit with two stable states that stores 1 bit. It is edge- or level-triggered by a clock.

SR flip-flop (NOR latch: S and R inputs, Q and Q’ outputs, cross-coupled)

JK flip-flop

D flip-flop: Qn+1 = D (0 → 0, 1 → 1).
T flip-flop: T = 0 → Qn (hold), T = 1 → Qn’ (toggle).

9. Counter and Shift Register

Counter: a sequential circuit that counts clock pulses and goes through a fixed sequence of states. A counter with n flip-flops has a maximum of 2ⁿ states (mod-2ⁿ).

• Asynchronous (ripple) counter: the clock is applied only to the first FF, and each FF triggers the next.
• Synchronous counter: all FFs share the same clock.
• Types: up, down, up/down, decade, ring, Johnson.

Shift register: a group of flip-flops connected in cascade that stores binary data and shifts it left or right on each clock pulse.

• Types: SISO, SIPO, PISO, PIPO.
• Uses: data storage, serial/parallel conversion, delay, counters.

10. Decoder and Encoder

Decoder: converts an n-bit binary input into a maximum of 2ⁿ unique outputs (only one output is active at a time).

2-to-4 decoder (with enable):

Y0 = A’B’, Y1 = A’B, Y2 = AB’, Y3 = AB (four AND gates plus two NOT gates).

Encoder: the reverse of a decoder. It has 2ⁿ inputs and n outputs, and gives the binary code of the active input.

4-to-2 encoder:

A = D2 + D3, B = D1 + D3 (two OR gates).

11. What is a Shift Register?

A shift register is a sequential circuit made of cascaded flip-flops, with the output of each FF connected to the input of the next, and all FFs driven by a common clock. Each clock pulse shifts the stored bits one position.

Serial in → [FF0]→[FF1]→[FF2]→[FF3] → Serial out
              ↑     ↑     ↑     ↑
              └─────── CLK ───────┘

An n-bit register uses n flip-flops. Data can be loaded and read serially or in parallel (SISO, SIPO, PISO, PIPO). It is used for temporary storage, data conversion, delays and counters.

12. Design of an 8×1 Multiplexer

There are 8 data inputs (I0–I7), 3 select lines (S2, S1, S0) and one output Y.

Y = S2’S1’S0’I0 + S2’S1’S0·I1 + S2’S1S0’I2 + S2’S1S0·I3 + S2S1’S0’I4 + S2S1’S0·I5 + S2S1S0’I6 + S2S1S0·I7

I0..I7 → eight 4-input AND gates (each also gets one
         decoded S2S1S0 combination) → 8-input OR → Y

Using smaller MUXes: two 4:1 MUXes (I0–I3 and I4–I7, both using S1, S0) feed a 2:1 MUX controlled by S2.

13. What is Gray Code?

Gray code is a non-weighted, unit-distance code in which only one bit changes between successive numbers. It is used in shaft encoders and K-map ordering, and it avoids errors during transitions.

Binary → Gray: the MSB stays the same, and each other Gray bit = XOR of the current and previous binary bits.

Gray → Binary: the MSB stays the same, and each next binary bit = previous binary bit XOR the current Gray bit.

14. Advantage of JK Flip-Flop over Clocked SR Flip-Flop

• The clocked SR flip-flop has an invalid (forbidden) state at S = R = 1, so its output is unpredictable.
• The JK flip-flop removes this condition: J = K = 1 makes the output toggle (Qn+1 = Qn’).
• So the JK is a universal flip-flop with all four input combinations valid. It can be converted into D or T flip-flops and used in counters.

15. Operational Characteristics of JK Flip-Flop

The JK flip-flop has inputs J, K and clock, and outputs Q and Q’. Its characteristic equation is Qn+1 = J·Qn’ + K’·Qn.

Race-around condition: when J = K = 1 and the clock pulse is wider than the propagation delay, the output toggles several times in one pulse. It is eliminated by using a master-slave JK flip-flop or an edge-triggered flip-flop, or by making the clock pulse narrower than the propagation delay.

16. De Morgan’s Law

Theorem 1: (A + B)’ = A’ · B’ (NOR = bubbled AND)
Theorem 2: (A · B)’ = A’ + B’ (NAND = bubbled OR)

Verification of Theorem 1 and Theorem 2:

The columns (A+B)’ and A’·B’ are identical, and so are (A·B)’ and A’+B’. Hence both laws are verified.

(A+B)' :  A ─┐          A ─[NOT]─┐
             [NOR]─ Y  =         [AND]─ Y
          B ─┘          B ─[NOT]─┘

(AB)'  :  A ─┐          A ─[NOT]─┐
             [NAND]─ Y =         [OR]─ Y
          B ─┘          B ─[NOT]─┘

17. Realizing AND, OR and NOT Using NAND

NOT:  A ─┬─[NAND]─ A'          (Y = (A·A)' = A')
         └─┘

AND:  A ─┐
         [NAND]─┬─[NAND]─ AB   (double inversion: ((AB)')' = AB)
      B ─┘      └─┘

OR:   A ─┬─[NAND]─┐
         └─┘      [NAND]─ A+B  (A'·B')' = A+B by De Morgan
      B ─┬─[NAND]─┘
         └─┘

Hence NAND alone can realize NOT, AND and OR, which is why it is a universal gate.

18. Sequential vs Combinational Logic

19. Ripple Counter

A ripple counter is an asynchronous counter in which the clock pulse is applied only to the first flip-flop, and the output of each flip-flop acts as the clock for the next one. The clock effect “ripples” through the stages.

3-bit up ripple counter (mod-8): three JK FFs (J = K = 1, in toggle mode) or T flip-flops.

CLK → [FF0]─Q0→[FF1]─Q1→[FF2]─Q2
       T=1      T=1      T=1

Count sequence: 000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000.

• Advantage: simple hardware.
• Disadvantage: the propagation delays add up, so it is slow and can show glitches. It is not suitable for high frequencies.
• A mod-N counter is made by using a NAND gate to reset the FFs when the count reaches N.

20. Bidirectional Shift Register

A bidirectional shift register can shift data both right and left, controlled by a mode input.

• Mode M = 1 → shift right
• Mode M = 0 → shift left

At each stage, a 2:1 MUX (or AND-OR gating) selects the D input of that flip-flop:

Di = M·Q(i−1) + M’·Q(i+1)

          ┌──[MUX]→[FF0]──┬──[MUX]→[FF1]── ...
Serial in │   ↑           │    ↑
(right)───┘   M           ...  M

• Right shift: each bit moves from Qi to Qi+1.
• Left shift: each bit moves from Qi to Qi−1.
• Universal shift register (e.g. IC 74194) adds parallel load as well