ARM LPC1768 Embedded C Programming and Architecture

Posted on Apr 28, 2026 in Computers

ARM LPC1768 Embedded C Programming Examples

LED Blinking Program for ARM LPC1768

#include <LPC17xx.h>

void delay() {
    for(int i=0; i<1000000; i++);
}

int main(void) {
    LPC_GPIO2->FIODIR |= (1<<0); // Set P2.0 as output
    while(1) {
        LPC_GPIO2->FIOSET = (1<<0); // LED ON
        delay();
        LPC_GPIO2->FIOCLR = (1<<0); // LED OFF
        delay();
    }
}

Switch Controlled LED Interfacing

#include <LPC17xx.h>

int main(void) {
    LPC_GPIO2->FIODIR |= (1<<0); // LED output
    LPC_GPIO1->FIODIR &= ~(1<<0); // Switch input

    while(1) {
        if(LPC_GPIO1->FIOPIN & (1<<0))
            LPC_GPIO2->FIOSET = (1<<0); // LED ON
        else
            LPC_GPIO2->FIOCLR = (1<<0); // LED OFF
    }
}

AC Appliance Relay Control Program

#include <LPC17xx.h>

int main() {
    LPC_GPIO2->FIODIR |= (1<<1);

    while(1) {
        LPC_GPIO2->FIOSET = (1<<1);
        delay_ms(2000);
        LPC_GPIO2->FIOCLR = (1<<1);
        delay_ms(2000);
    }
}

DC Motor Direction Control Logic

int main() {
    LPC_GPIO2->FIODIR |= (1<<0)|(1<<1);

    while(1) {
        // Forward
        LPC_GPIO2->FIOSET = (1<<0);
        LPC_GPIO2->FIOCLR = (1<<1);
        delay_ms(2000);

        // Reverse
        LPC_GPIO2->FIOCLR = (1<<0);
        LPC_GPIO2->FIOSET = (1<<1);
        delay_ms(2000);
    }
}

Essential Embedded C Commands

GPIO Configuration Commands

• Set P2.0 as Output: LPC_GPIO2->FIODIR |= (1<<0);
• Set P1.0 as Input: LPC_GPIO1->FIODIR &= ~(1<<0);
• Turn ON LED: LPC_GPIO2->FIOSET = (1<<0);
• Turn OFF LED: LPC_GPIO2->FIOCLR = (1<<0);
• Check Switch State: if(LPC_GPIO1->FIOPIN & (1<<0));

ARM Processor Classifications

• Cortex-M Series: For microcontrollers (low power, real-time control)
• Cortex-R Series: For real-time systems (e.g., automotive, robotics)
• Cortex-A Series: For application processors (e.g., smartphones, tablets)
• Neoverse: For infrastructure and cloud computing
• Apple Silicon (e.g., M1, M2): Custom ARM-based processors for Macs

Industry Applications of ARM

• Consumer Electronics: Smartphones, smart TVs
• Industrial Automation: PLCs, controllers
• Automotive: ABS, airbags, ECUs
• Medical: ECG, patient monitors
• IoT: Smart meters, sensors
• Robotics: Motor controllers

ARM Architecture Features and Applications

ARM (Advanced RISC Machine) is a 32-bit / 64-bit RISC processor architecture widely used in embedded systems, mobile phones, IoT devices, automotive, and industrial controllers.

ARM does not manufacture chips; it licenses designs. Companies like ST, NXP, TI, and Qualcomm manufacture the actual chips.

Key Features of ARM RISC Architecture

• RISC architecture
• Low power consumption
• High performance per watt
• Load–Store architecture
• Large register set
• Pipeline execution
• Supports Thumb instruction set

ARM follows the RISC (Reduced Instruction Set Computer) philosophy, focusing on simplicity, high performance, low power consumption, and efficient code execution.

Core Design Goals

• Fewer, simpler instructions
• Most instructions execute in a single clock cycle
• Use of load–store architecture
• Heavy use of registers instead of memory

ARM Register Set and Special Registers

General Purpose and Status Registers

• R0–R12: General purpose registers
• R13: Stack Pointer (SP)
• R14: Link Register (LR)
• R15: Program Counter (PC)
• CPSR: Current Program Status Register

CPSR (Current Program Status Register)

The CPSR controls the following flags:

• Zero flag
• Carry flag
• Negative flag
• Overflow
• Interrupt enable/disable

Special Purpose Registers in ARM

Stack Pointer (SP – R13): There are two stack pointers: MSP (Main Stack Pointer) and PSP (Process Stack Pointer). MSP is used after reset.

Link Register (LR – R14): Stores the return address and is used during subroutine calls and interrupt handling.

Program Counter (PC – R15): Holds the address of the next instruction and is auto-incremented.

xPSR Register Components

• APSR: Condition flags
• EPSR: Execution status
• IPSR: Interrupt number

ARM Cortex-M3 Architecture and Memory

Cortex-M3 Processor Core Components

• Interrupt Controller (NVIC)
• Instruction Fetch Unit
• Decoder
• Register Bank
• ALU
• Memory Interface
• Debug System
• Trace Interface
• Memory Protection Unit
• Bus Interconnect
• Debug Interface

Memory Regions and Bus Interconnect

• Code: Program storage
• SRAM: Data storage
• Peripheral: GPIO, timers
• System: NVIC, SysTick

The Cortex-M3 architecture diagram illustrates the Processor Core System connected to the memory system and peripherals through a bus interconnect, including the NVIC, ALU, register bank, instruction fetch unit, decoder, debug system, and memory interface.