8085 Microprocessor Activity Sheet Solutions

Posted on Jul 17, 2026 in Aerospace Engineering

Thakur College of Science and Commerce

SYJC Computer Science II – Activity Sheet No. 1

Answers (Page 1 & 2)

I. Choose the Correct Alternative

  • 1) _________ is 8 bit non accessible register.
    Answer: (c) IR (Instruction Register)
  • 2) __________ is an example of 16 bit accessible register of MP 8085.
    Answer: (b) SP (Stack Pointer)
  • 3) __________ register pair acts as a memory pointer.
    Answer: (b) HL
  • 4) After fetching an instruction from memory, it is stored in ___________.
    Answer: (b) Instruction Register
  • 5) After doing any arithmetic & logical instruction in ALU, the result is stored in ___________.
    Answer: (a) Accumulator
  • 6) If answer is having even parity, then Parity flag will _________.
    Answer: (a) Set
  • 7) In flag register _________ bits are unused.
    Answer: (b) 3
  • 8) __________ register of MP 8085 is used only during arithmetic & logical instructions and not for any other purpose.
    Answer: (b) Temporary Register
  • 9) _________ register is not a general purpose register.
    Answer: (c) F (Flag Register)
  • 10) ___________ block of MP 8085 is responsible for serial communication.
    Answer: (a) Serial I/O Control Unit
  • 11) Internal data bus of MP 8085 is __________ bit long.
    Answer: (a) 8
  • 12) When IO/M is low, it denotes the ______ related operation of MP 8085.
    Answer: (c) Memory
  • 13) To demultiplex address & data bus of MP 8085 __________ pin is used.
    Answer: (d) ALE
  • 14) In response to __________ interrupt, MP 8085 generates INTA signal.
    Answer: (d) INTR
  • 15) DMA controller is requesting the use of address & data bus by sending __________ signal.
    Answer: (a) HOLD
  • 16) __________ is not an active low signal of MP 8085.
    Answer: (c) RESET OUT
  • 17) ______ instructions are available in MP 8085 instruction set.
    Answer: (b) 74
  • 18) _________ is non maskable interrupt.
    Answer: (b) TRAP
  • 19) ________ is used to communicate with slow peripheral devices.
    Answer: (a) READY

II. Answer the Following

Q1) Describe the following pins of MP 8085.

(a) ALE

Status: Outgoing
Function: ALE (Address Latch Enable) is used to demultiplex the lower address and data bus (AD0–AD7). During the first T-state, it enables the latch to store the lower address.

(b) RD

Status: Outgoing (Active Low)
Function: RD indicates that the selected memory or I/O location is to be read. When RD becomes LOW, data is available on the data bus.

(c) TRAP

Status: Incoming
Priority: Highest (Priority 1)
Maskable / Non-maskable: Non-maskable
Vectored / Non-vectored: Vectored
Vector Address: 0024H

(d) READY

Status: Incoming
Function: READY is used to synchronize the 8085 with slow peripheral devices. If READY is LOW, the microprocessor inserts wait states until the device becomes ready.

Q2) Write function of the following blocks of MP 8085.

(a) Accumulator

Type: 8-bit Accessible Register. It is considered a part of ALU.
Function: It stores one operand for arithmetic and logical operations and also stores the result obtained from the ALU.

(b) IR (Instruction Register)

Type: 8-bit Non-accessible Register
Function: It stores the opcode of the fetched instruction and sends it to the Instruction Decoder for decoding.

(c) Serial I/O Control Unit

It controls serial communication of MP 8085 using SID (Serial Input Data) and SOD (Serial Output Data).

Q3) Draw flag data structure & explain each flag bit.

D7D6D5D4D3D2D1D0
SZXACXPXCY

(X = Unused Bits)

  • Sign Flag (S): Set to 1 if the result is negative.
  • Zero Flag (Z): Set to 1 if the result is zero.
  • Auxiliary Carry Flag (AC): Set if carry is generated from D3 to D4.
  • Parity Flag (P): Set to 1 if the result has even parity.
  • Carry Flag (CY): Set if carry is generated from the MSB.

Q4. Explain the working of status pins S0 and S1 along with IO/M pin.

The status pins S0, S1 and IO/M indicate the type of machine cycle being performed by the 8085.

  • IO/M = 0: Memory operation.
  • IO/M = 1: I/O operation.

Q5. Maskable, Non-maskable and Vectored Interrupts

  • Maskable: Can be disabled using EI/DI instructions (e.g., RST 7.5).
  • Non-maskable: Cannot be disabled (e.g., TRAP).
  • Vectored: Transfers control to a fixed memory location (e.g., TRAP).

Q6. Hardware Interrupt System

The 8085 has five hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. Priority order: TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR.

Q7. Address and Data Bus Structure

The 8085 features a 16-bit address bus and an 8-bit data bus. Higher-order lines (A8–A15) are unidirectional, while lower-order lines (AD0–AD7) are multiplexed.

Q8. Multiplexing of Address and Data Bus

Multiplexing uses pins AD0–AD7 for both address and data. Advantages: Reduced pin count, compact circuit, less wiring. Disadvantages: Requires external latch, slower speed due to demultiplexing time.