VHDL Programming: Operators, Data Types, and Modeling

Posted on Jun 13, 2026 in Civil Engineering, Transportation, and Urban Services

VHDL Operators and Classifications

Operators in VHDL are special symbols used to perform operations on data. They are used for logical, arithmetic, comparison, shifting, and assignment operations. The operators in VHDL are classified as:

  • 1. Assignment Operators
  • 2. Logical Operators
  • 3. Arithmetic Operators
  • 4. Relational Operators
  • 5. Shift Operators
  • 6. Concatenation Operator

1. Assignment Operators

Purpose:

  • <= : Signal assignment
  • := : Variable assignment
  • => : Association operator

Example: x <= '1'; count := count + 1;

2. Logical Operators

Purpose: Logical operators perform Boolean operations.

Functions: NOT (Inversion), AND (Logical AND), OR (Logical OR), NAND (NOT AND), NOR (NOT OR), XOR (Exclusive OR), XNOR (Exclusive NOT).

Example: sum <= a XOR b; out1 <= a AND b;

3. Arithmetic Operators

Purpose: Used for mathematical calculations.

Operators and Functions:

  • + : Addition
  • - : Subtraction
  • * : Multiplication
  • / : Division
  • MOD : Modulus
  • REM : Remainder

Example: sum <= a + b; diff <= a - b;

4. Relational Operators

Purpose: Used for comparison operations.

Operators and Functions:

  • = : Equal to
  • /= : Not equal to
  • < : Less than
  • > : Greater than
  • <= : Less than or equal
  • >= : Greater than or equal

Example: IF (a = b) THEN

5. Shift Operators

Purpose: Used for shifting bits.

Operators and Functions:

  • sll : Shift left logical
  • srl : Shift right logical
  • sla : Shift left arithmetic
  • sra : Shift right arithmetic
  • rol : Rotate left
  • ror : Rotate right

Example: y <= x sll 2;

6. Concatenation Operator

Purpose: The concatenation operator joins vectors or bits.

Operator: &

Example: z <= a & b;

Thus, operators in VHDL are used to perform assignment, logical, arithmetic, comparison, shifting, and concatenation operations for efficient hardware modelling.

Scalar Data Types in VHDL

Scalar data types store a single value at a time. The values are arranged in sequential order. Scalar data types are classified into:

1. Enumeration Types

Contains a list of identifiers or character literals.

Syntax: TYPE COLOR IS (RED, GREEN, BLUE);

Important predefined enumeration types:

  • BIT Type: TYPE BIT IS ('0','1');
  • BOOLEAN Type: TYPE BOOLEAN IS (FALSE, TRUE);
  • STD_LOGIC Type: ('U','X','0','1','Z','W','L','H','-'). STD_LOGIC is the most commonly used VHDL data type.

2. Integer Type

Integer type represents whole numbers.

Example: TYPE COUNT IS RANGE 0 TO 255;

Predefined range: -2,147,483,647 to +2,147,483,647

3. Real Type

Real type represents floating point numbers.

Example: VARIABLE x : REAL := 10.5;

Range: -1.0E+38 to +1.0E+38

4. Physical Type

Physical types represent physical quantities such as time, voltage, and current.

Example: SIGNAL delay : TIME := 10 ns;

Scalar data types in VHDL are used to represent logic values, integers, real numbers, and physical quantities during hardware modelling.

Literals, Attributes, and Data Objects

Literals

Literals are constant values used in VHDL. Types of literals include:

  1. Numeric literals
  2. Character literals
  3. Enumeration literals
  4. String literals

Example: 25, '1', "1010"

Attributes

Attributes are predefined properties used to obtain information about signals, arrays, and data types.

Example: clk'EVENT, x'LENGTH

Important Attributes and Meanings:

  • 'EVENT: Detects signal change
  • 'LENGTH: Returns size
  • 'RANGE: Returns range
  • 'HIGH: Highest value
  • 'LOW: Lowest value

Data Objects

Data objects are entities that hold values during program execution. Types include:

  1. Signals: SIGNAL a : STD_LOGIC;
  2. Variables: VARIABLE count : INTEGER;
  3. Constants: CONSTANT pi : REAL := 3.14;
  4. Files

Arrays in VHDL

An array is a collection of elements of the same data type.

Syntax: TYPE array_name IS ARRAY(range) OF data_type;

One-Dimensional Array

Contains only one index. Used for vectors and registers.

Example: TYPE vector IS ARRAY(0 TO 7) OF STD_LOGIC;

Two-Dimensional Array

Contains rows and columns. Used for memories and matrices.

Example: TYPE matrix IS ARRAY(0 TO 3, 0 TO 3) OF STD_LOGIC;

Difference Between 1D and 2D Arrays

  • 1D Array: Single index, vector structure, simpler.
  • 2D Array: Two indices, matrix structure, more complex.

Arrays in VHDL are composite data types used for storing collections of similar elements.

VHDL Design Examples

Positive Edge Triggered D Flip-Flop

D Flip-Flop with synchronous reset using a guarded block:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY dff IS
PORT(
   clk, rst, d : IN STD_LOGIC;
   q : OUT STD_LOGIC
);
END dff;

ARCHITECTURE guarded OF dff IS
BEGIN
   b1 : BLOCK(clk'EVENT AND clk='1')
   BEGIN
      q <= GUARDED '0' WHEN rst='1' ELSE d;
   END BLOCK b1;
END guarded;

1-Bit Comparator Modeling Styles

Dataflow Modelling

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY comparator IS
PORT(
   a, b : IN STD_LOGIC;
   eq : OUT STD_LOGIC
);
END comparator;

ARCHITECTURE dataflow OF comparator IS
BEGIN
   eq <= a XNOR b;
END dataflow;

Behavioral Modelling

ARCHITECTURE behavioral OF comparator IS
BEGIN
PROCESS(a, b)
BEGIN
   IF(a = b) THEN
      eq <= '1';
   ELSE
      eq <= '0';
   END IF;
END PROCESS;
END behavioral;

Structural Modelling

ARCHITECTURE structural OF comparator IS
COMPONENT xnor_gate
PORT(
   x, y : IN STD_LOGIC;
   z : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
   U1 : xnor_gate
   PORT MAP(a, b, eq);
END structural;

Full Adder Using Behavioral Modelling

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY fulladder IS
PORT(
   a, b, carry_in : IN STD_LOGIC;
   sum, carry_out : OUT STD_LOGIC
);
END fulladder;

ARCHITECTURE behavioral OF fulladder IS
BEGIN
PROCESS(a, b, carry_in)
BEGIN
   IF(a='0' AND b='0' AND carry_in='0') THEN
      sum <= '0'; carry_out <= '0';
   ELSIF(a='0' AND b='0' AND carry_in='1') THEN
      sum <= '1'; carry_out <= '0';
   ELSIF(a='0' AND b='1' AND carry_in='0') THEN
      sum <= '1'; carry_out <= '0';
   ELSIF(a='0' AND b='1' AND carry_in='1') THEN
      sum <= '0'; carry_out <= '1';
   ELSIF(a='1' AND b='0' AND carry_in='0') THEN
      sum <= '1'; carry_out <= '0';
   ELSIF(a='1' AND b='0' AND carry_in='1') THEN
      sum <= '0'; carry_out <= '1';
   ELSIF(a='1' AND b='1' AND carry_in='0') THEN
      sum <= '0'; carry_out <= '1';
   ELSE
      sum <= '1'; carry_out <= '1';
   END IF;
END PROCESS;
END behavioral;

8-Input NAND Gate Using Loop Statement

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY nand8 IS
GENERIC(n : INTEGER := 8);
PORT(
   input : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
   nandout : OUT STD_LOGIC
);
END nand8;

ARCHITECTURE bhvloop OF nand8 IS
BEGIN
PROCESS(input)
VARIABLE temp : STD_LOGIC := '1';
BEGIN
   temp := '1';
   FOR i IN 0 TO n-1 LOOP
      temp := temp AND input(i);
   END LOOP;
   nandout <= NOT temp;
END PROCESS;
END bhvloop;

VHDL Coding Styles

The four main VHDL coding styles are:

  1. Behavioral Modelling: Describes what the circuit does using PROCESS and sequential statements.
  2. Dataflow Modelling: Describes the flow of data using Boolean equations.
  3. Structural Modelling: Describes the interconnection of components.
  4. Mixed Modelling: A combination of behavioral, dataflow, and structural styles.

Different VHDL coding styles provide different abstraction methods for efficient hardware design.

Testbench in VHDL

A Testbench is a VHDL model used to test and verify the correctness of a digital circuit. The circuit being tested is called the DUT (Device Under Test). Important features include:

  • 1. Verifies circuit operation
  • 2. Detects design errors
  • 3. Generates input stimulus
  • 4. Observes output response
  • 5. Improves reliability

Full Adder Testbench Code

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_fulladder IS
END tb_fulladder;

ARCHITECTURE behavior OF tb_fulladder IS
COMPONENT fulladder
PORT(
   a, b, cin : IN STD_LOGIC;
   sum, carry : OUT STD_LOGIC
);
END COMPONENT;

SIGNAL a, b, cin, sum, carry : STD_LOGIC;
BEGIN
   UUT : fulladder PORT MAP(a, b, cin, sum, carry);
   stim_proc : PROCESS
   BEGIN
      a <= '0'; b <= '0'; cin <= '0'; WAIT FOR 10 ns;
      a <= '0'; b <= '0'; cin <= '1'; WAIT FOR 10 ns;
      a <= '0'; b <= '1'; cin <= '0'; WAIT FOR 10 ns;
      a <= '0'; b <= '1'; cin <= '1'; WAIT FOR 10 ns;
      a <= '1'; b <= '0'; cin <= '0'; WAIT FOR 10 ns;
      a <= '1'; b <= '0'; cin <= '1'; WAIT FOR 10 ns;
      a <= '1'; b <= '1'; cin <= '0'; WAIT FOR 10 ns;
      a <= '1'; b <= '1'; cin <= '1'; WAIT FOR 10 ns;
      WAIT;
   END PROCESS;
END behavior;

Functions and Procedures

Function

A function is a reusable subprogram that returns exactly one value.

Example:

FUNCTION maximum(a, b : INTEGER) RETURN INTEGER IS
BEGIN
   IF a > b THEN RETURN a;
   ELSE RETURN b;
   END IF;
END;

Procedure

A procedure is a reusable subprogram that performs operations and may return multiple values through OUT parameters.

Example:

PROCEDURE add(a, b : IN INTEGER; sum : OUT INTEGER) IS
BEGIN
   sum := a + b;
END;

Difference Between Function and Procedure

  • Function: Returns one value, used in expressions, RETURN is compulsory.
  • Procedure: No direct return (uses parameters), used as a statement, RETURN is optional.

Delays in VHDL

Delay is the time required for a signal to propagate from input to output. Types of delays include:

  1. Transport Delay: Transfers all pulses. Example: q <= TRANSPORT a AFTER 10 ns;
  2. Inertial Delay: Rejects short pulses. It is the default delay model. Example: q <= a AFTER 10 ns;
  3. Delta Delay: Infinitesimally small simulator delay used for event ordering. Example: a <= NOT x;

Comparison of Delay Models

  • Transport: Propagates all pulses.
  • Inertial: Filters small pulses.
  • Delta: Controls simulation order.

Thus, VHDL delay models are used to simulate practical hardware timing behavior accurately.

4×1 Multiplexer Implementations

Using Behavioral Modeling

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY mux4x1 IS
PORT(
   d0, d1, d2, d3 : IN STD_LOGIC;
   s0, s1 : IN STD_LOGIC;
   y : OUT STD_LOGIC
);
END mux4x1;

ARCHITECTURE behavioral OF mux4x1 IS
BEGIN
PROCESS(d0, d1, d2, d3, s0, s1)
BEGIN
   IF(s1='0' AND s0='0') THEN y <= d0;
   ELSIF(s1='0' AND s0='1') THEN y <= d1;
   ELSIF(s1='1' AND s0='0') THEN y <= d2;
   ELSE y <= d3;
   END IF;
END PROCESS;
END behavioral;

Using With-Select Statement

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY mux4x1 IS
PORT(
   d0, d1, d2, d3 : IN STD_LOGIC;
   sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
   y : OUT STD_LOGIC
);
END mux4x1;

ARCHITECTURE with_select OF mux4x1 IS
BEGIN
WITH sel SELECT
   y <= d0 WHEN "00",
        d1 WHEN "01",
        d2 WHEN "10",
        d3 WHEN OTHERS;
END with_select;