VHDL Code Examples for Digital Logic Circuits
bit ALU
Entity ALU is
Port ( A, B : in STD_LOGIC_VECTOR (3 downto 0);
OP : in STD_LOGIC_VECTOR (1 downto 0);
Result : out STD_LOGIC_VECTOR (3 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(A, B, OP)
begin
case OP is
when “00” => Result
when “01” => Result
when “10” => Result
when “11” => Result
when others => Result
end case;
end process;
end Behavioral;
MUX Using When Else Statement
entity MUX41 is
Port ( I0, I1, I2, I3 : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC);
end MUX41;
architecture Behavioral of MUX41 is
begin
Y
I1 when S = “01” else
I2 when S = “10” else
I3;
end Behavioral;
MUX Using With Select
entity MUX41 is
Port ( I0, I1, I2, I3 : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC);
end MUX41;
architecture Behavioral of MUX41 is
begin
with S select
Y
I1 when “01”,
I2 when “10”,
I3 when others;
end Behavioral;
Decoder Using When Else
entity Decoder24 is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end Decoder24;
architecture Behavioral of Decoder24 is
begin
Y
“0010” when A = “01” else
“0100” when A = “10” else
“1000”;
end Behavioral;
Decoder Using With Select
entity Decoder24 is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end Decoder24;
architecture Behavioral of Decoder24 is
begin
with A select
Y
“0010” when “01”,
“0100” when “10”,
“1000” when others;
end Behavioral;
T Flip-Flop
entity T_FlipFlop is
Port ( T, CLK, RST : in STD_LOGIC;
Q, Qbar : out STD_LOGIC);
end T_FlipFlop;
architecture Behavioral of T_FlipFlop is
signal State : STD_LOGIC;
begin process(T, CLK, RST) begin
if RST = ‘1’ then state
elsif rising_edge(CLK) then
if T = ‘0’ then state
elsif T = ‘1’ then state
end if; end if; end process;
Q
Qbar
D Flip-Flop
entity DFF is
Port ( D, CLK, RST : in STD_LOGIC;
Q : out STD_LOGIC);
end DFF;
architecture Behavioral of DFF is
begin process(CLK, RST) begin
if RST = ‘1’ then Q
elsif rising_edge(CLK) then Q
end if; end process; end Behavioral;
JK Flip-Flop
entity JKFF is
Port ( J, K, CLK, RST : in STD_LOGIC;
Q, Qbar : out STD_LOGIC);
end JKFF;
architecture Behavioral of JKFF is
signal State : STD_LOGIC;
begin process(CLK, RST) begin
if RST = ‘1’ then State
elsif rising_edge(CLK) then
if J = ‘0’ and K = ‘0’ then State
elsif J = ‘0’ and K = ‘1’ then State
elsif J = ‘1’ and K = ‘0’ then State
elsif J = ‘1’ and K = ‘1’ then
State
end if; end if; end process;
Q
Qbar
end Behavioral;
bit Up Counter
entity UpCounter is
Port ( CLK, RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end UpCounter;
architecture Behavioral of UpCounter is
begin process(CLK, RST)
variable State : STD_LOGIC_VECTOR (3 downto 0) := “0000”;
begin
if RST = ‘1’ then State := “0000”;
elsif rising_edge(CLK) then
State := State + 1;
end if;
Q
bit Down Counter
entity DownCounter is
Port ( CLK, RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end DownCounter;
architecture Behavioral of DownCounter is
begin process(CLK, RST)
variable temp : unsigned (3 downto 0) := “1111”;
begin
if RST = ‘1’ then temp := “1111”;
elsif rising_edge(CLK) then temp := temp – 1;
end if;
Q
end process;
end Behavioral;
bit Up-Down Counter
entity UpDownCounter is
Port ( DIR, CLK, RST : in STD_LOGIC;
Cout : out STD_LOGIC_VECTOR (3 downto 0));
end UpDownCounter;
architecture Behavioral of UpDownCounter is
begin process(CLK, RST)
variable temp : unsigned (3 downto 0) := “0000”;
begin
if RST = ‘1’ then temp := “0000”;
elsif rising_edge(CLK) then
if DIR = ‘1’ then temp := temp + 1;
else temp := temp – 1;
end if; end if;
Cout
end process; end Behavioral;
bit Comparator
entity Comparator4bit is
Port ( A, B : in STD_LOGIC_VECTOR (3 downto 0);
EN : in STD_LOGIC;
alb, agb, aeb : out STD_LOGIC);
end Comparator4bit;
architecture Behavioral of Comparator4bit is
begin process(A, B, EN) begin if EN = ‘1’ then
if A = B then alb
elsif A > B then alb
else alb
else alb
end if; end process; end Behavioral;
Mod 10 Counter
entity Mod10Counter is
Port ( CLK, RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Mod10Counter;
architecture Behavioral of Mod10Counter is
begin process(CLK, RST)
variable temp : unsigned (3 downto 0) := “0000”;
begin if RST = ‘1’ then temp := “0000”;
elsif rising_edge(CLK) then temp := temp + 1;
if temp = “1010” then temp := “0000”;
end if; end if;
Q
end process; end Behavioral;
PIPO Shift Register
Entity PIPO is
Port(D: In std_logic_vector(3 downto 0);
Clk, rst: In std_logic;
Pout: Out std_logic_vector(3 downto 0));
End PIPO;
Architecture behavioral of PIPO is
Signal Q: std_logic_vector(3 downto 0);
Begin Process (Clk,rst) Begin
If (rst = ‘1’) then Q ‘0’);
Elseif (clk’event and clk = ‘1’) then Q
End if; End process;
Pout
SISO Shift Register
Entity SISO is
Port (Sin, clk, rst: In std_logic; Sout: out std_logic);
End SISO;
Architecture behavioral of SISO is
Signal T2, T1, T0: std_logic;
Begin process (Sin, clk, rst) Begin
If (rst=’1′) then
Sout
Elseif (clk’event and clk= ‘1’) then
Sout
End if;
End process;
End behavioral;