Verilog HDL, Memory Systems, and Error Correction Codes

Posted on Sep 15, 2025 in Computers

Verilog HDL Lexical Conventions

Lexical conventions in Verilog define the basic rules for writing code. They include whitespace, comments, identifiers, keywords, numbers, strings, and operators. These elements form the fundamental structure of Verilog programs.

1. Whitespace

• Spaces, tabs, and newlines enhance readability.
• Ignored by the compiler/simulator except when part of a string literal.

2. Comments

• // for single-line comments.
• /* */ for multi-line comments.
• Used to describe code; they are not part of the logic.

3. Operators

• Symbols like +, -, *, &&, ||, ==.
• Used for arithmetic, logical, and bitwise operations.

4. Numbers

• Format: size'basevalue (e.g., 4'b1010).
• Supports binary, decimal, octal, and hexadecimal bases.

5. Strings

• Text enclosed in double quotes (e.g., "Hello World").
• Primarily used with system tasks like $display and $monitor for simulation output.

6. Identifiers

• Names for variables, modules, functions, etc.
• Must start with a letter or an underscore (_), not a digit.

7. Keywords

• Reserved words like module, input, assign.
• Cannot be used as user-defined variable or module names.

Verilog HDL System Tasks

System tasks in Verilog are special built-in commands used to control simulation, display output, manage timing, and perform debugging. They begin with a dollar sign ($) and are only used during simulation — they are generally not synthesizable.

Commonly Used System Tasks:

$display

Prints messages or variable values to the console, automatically adding a newline character.

Example: $display("a = %b", a);

$monitor

Continuously displays variable changes during simulation. A new line is printed whenever any monitored variable changes value.

Example: $monitor("time = %0t, a = %b", $time, a);

$time

Returns the current simulation time, often used for debugging and timing analysis.

Example: $display("Current time = %0t", $time);

$finish

Ends the simulation immediately.

Example: $finish;

$stop

Pauses the simulation and allows for inspection or interactive debugging.

Example: $stop;

$write

Similar to $display but does not add a newline character at the end of the output.

Example: $write("a = %b", a);

$dumpfile and $dumpvars

Used together to generate waveform output files (e.g., VCD format) for viewing in waveform viewers like GTKWave.

Example:

$dumpfile("wave.vcd");
$dumpvars(0, testbench_name);

Verilog Data Types Explained

Data types in Verilog define how variables, signals, and constants are declared and used. They are crucial for modeling digital systems by specifying how data is stored, transferred, and processed.

Net Data Types

Used to represent physical connections like wires. Their value is continuously driven by other sources (e.g., gates, modules).

Example:

wire a;
wire [3:0] data_bus;

Register (reg) Data Type

Stores a value until it is explicitly changed by an assignment within procedural blocks (like always or initial blocks).

Example:

reg clk;
reg [7:0] counter;

Integer and Real Data Types

• Integer: Used for whole numbers.
• Real: Used for decimal values (primarily for simulation and not synthesizable).

Example:

integer count;
real voltage;

Vectors

Used to define multi-bit buses or groups of signals. They can be used with both net and reg types.

Example:

wire [7:0] data_in;
reg [3:0] control;

Constants (parameter)

Used to define fixed values that do not change during simulation or synthesis. They improve code readability and reusability.

Example:

parameter WIDTH = 8;

Arrays

Used to declare a group of related variables or signals, often representing memory blocks.

Example:

reg [7:0] mem_array [0:15]; // 16 memory locations, each 8-bit wide

Strings

Used to store and display character data, mainly for simulation and debugging purposes.

Example:

reg [80*8:1] msg = "Test Complete";
// Or using SystemVerilog:
string my_text = "Hello";

Enumerations (SystemVerilog)

Used to define a set of named values for better code readability and maintainability (a SystemVerilog feature).

Example:

typedef enum {IDLE, READ, WRITE} state_t;
state_t current_state;

Asynchronous vs. Synchronous SRAM

Static RAM (SRAM) can be categorized based on its timing control. Here’s a comparison between asynchronous and synchronous SRAM:

Asynchronous Static RAM

• Clock Requirement: No clock signal is required for operation.
• Operation Speed: Generally slower due to reliance on control signal propagation delays.
• Control Signals: Uses control signals like Chip Enable (CE), Output Enable (OE), and Write Enable (WE).
• Access Time: Variable access time, depending on the control signal transitions.
• Typical Use: Found in microcontrollers, small embedded systems, and cache memory where simplicity is prioritized.
• Power Consumption: Often has lower power consumption in idle states.
• Design Complexity: Simpler design due to the absence of clock synchronization logic.

Synchronous Static RAM

• Clock Requirement: Requires a clock signal for all operations.
• Operation Speed: Faster and more predictable operation, as all actions are synchronized to the clock edge.
• Control Signals: Uses a clock along with other control signals (e.g., Clock Enable, Write Enable).
• Access Time: Fixed access time, determined by the clock cycle.
• Typical Use: Employed in high-performance processors, FPGAs, and high-speed systems where precise timing is critical.
• Power Consumption: Generally higher power consumption due to continuous clocking.
• Design Complexity: More complex design due to the need for precise timing control and synchronization logic.

ECC Word Error Detection and Correction

Let’s determine if there is an error in the given ECC word and correct it using Hamming code principles.

Given ECC word: 000111000100 (12 bits)

Steps for Correction:

Step 1: Identify Parity Bits

Parity bits are typically located at positions 1, 2, 4, 8 (powers of 2).

Step 2: Check Parity using Even Parity Rules

We’ll calculate the parity for each parity bit’s group and compare it to the actual parity bit in the ECC word.

• P1 (positions 1, 3, 5, 7, 9, 11):
  Bits: ECC[1], ECC[3], ECC[5], ECC[7], ECC[9], ECC[11]
  Values: 0, 0, 1, 0, 0, 0
  XOR sum: 0^0^1^0^0^0 = 1
  Actual P1 (ECC[1]) is 0. Expected P1 is 1. Error detected in P1.
• P2 (positions 2, 3, 6, 7, 10, 11):
  Bits: ECC[2], ECC[3], ECC[6], ECC[7], ECC[10], ECC[11]
  Values: 0, 0, 1, 0, 1, 0
  XOR sum: 0^0^1^0^1^0 = 0
  Actual P2 (ECC[2]) is 0. Expected P2 is 0. Correct.
• P3 (positions 4, 5, 6, 7, 12):
  Bits: ECC[4], ECC[5], ECC[6], ECC[7], ECC[12]
  Values: 1, 1, 1, 0, 0
  XOR sum: 1^1^1^0^0 = 1
  Actual P3 (ECC[4]) is 1. Expected P3 is 1. Correct.
• P4 (positions 8, 9, 10, 11, 12):
  Bits: ECC[8], ECC[9], ECC[10], ECC[11], ECC[12]
  Values: 0, 0, 1, 0, 0
  XOR sum: 0^0^1^0^0 = 1
  Actual P4 (ECC[8]) is 0. Expected P4 is 1. Error detected in P4.

The error syndrome is formed by combining the parity check results (P4 P3 P2 P1). If P1 is incorrect, it contributes 1 to the syndrome. If P4 is incorrect, it contributes 8. So, the error syndrome is 1001 (binary) which is 9 (decimal).

This indicates an error at position 9.

Step 3: Flip Bit at Position 9

The bit at position 9 in the original ECC word is 0. Flipping it changes it to 1.

Original ECC word: 000111000100
Corrected ECC word: 000111001100

Therefore, an error was detected at position 9, and it has now been corrected.

Memory Components and Multiport RAM

A basic memory component, like RAM, stores data temporarily and allows both read and write operations. It consists of several key parts.

Basic Memory Components

Address Bus

Carries the address of the specific memory location to be accessed.

Example: An address[3:0] bus can access 16 unique memory locations.

Address Decoder

Selects a specific memory cell or row based on the input address from the address bus.

Example: A 4-to-16 decoder activates one of 16 rows in a 16-location memory.

Data Input (DIN)

Carries the data to be written into the memory at the selected address.

Example: DIN = 8'b10101100

Data Output (DOUT)

Carries the data read from the selected memory location to the external system.

Example: DOUT = 8'b11001100

Read Enable (RE) or Read Control Signal

An active-high or active-low signal that activates the read operation when asserted.

Example: RE = 1 allows data to be sent from memory to the output.

Write Enable (WE)

An active-high or active-low signal that activates the write operation when asserted.

Example: WE = 1 and RE = 0 stores the input data to the selected location.

Memory Cells

The fundamental storage units (e.g., flip-flops or latches in SRAM) arranged in rows and columns to store individual bits.

Example: A 4×8 RAM has 4 locations, each capable of storing 8 bits.

Control Signals

Additional signals used to control timing, chip selection (CS), clocking, and other memory operations.

Example: CS (Chip Select) must be active for any memory access to occur.

Multiport Memory

Multiport memory allows more than one read or write operation to occur simultaneously through multiple independent ports. This significantly improves performance in parallel processing systems by reducing access bottlenecks.

Types of Multiport Memory:

1. Dual-Port Memory: Has two independent ports that can access the memory simultaneously. Each port typically has its own address, data, and control lines. Example: One port can perform a read operation while the other performs a write operation.
2. Multiport Register File: A small, very fast memory with multiple read and write ports. Commonly used in CPUs for storing general-purpose registers. Example: A register file with two read ports and one write port.
3. True Multiport RAM: Each port can read and write independently at the same time. These are more complex and expensive due to the necessary arbitration and conflict resolution logic.

Advantages of Multiport Memory:

• Allows simultaneous access by multiple processing units or functional blocks.
• Significantly improves data throughput and overall system speed.
• Ideal for parallel computing and pipelined architectures.
• Reduces memory access bottlenecks in high-performance processors and systems.

Hamming Code Check Bits for SEC-DED

Let’s determine the number of check bits required for single error correction (SEC) and double error detection (DED) for a 4-bit data word using Hamming code.

Formula for SEC-DED Hamming Code:

For a data word of k bits and r check bits, the total number of bits in the codeword is n = k + r + 1. The extra +1 bit is for an overall parity bit, which enables double error detection.

We need to satisfy the condition:

2^r ≥ k + r + 1

Here, k = 4 (number of data bits).

Calculation for 4-bit Data Word:

• Try r = 3:
  2^3 = 8
k + r + 1 = 4 + 3 + 1 = 8
  Since 8 ≥ 8, the condition is satisfied.

This means 3 check bits are needed for single error correction, and an additional 1 bit is required for overall parity to achieve double error detection.

Final Answer: 4 check bits (3 for SEC + 1 for DED) are required for single error correction and double error detection of a 4-bit data word using Hamming code.

Verilog Compiler Directives

Compiler directives in Verilog are special commands that begin with a backtick (`) and control how the compiler processes the code. They do not describe hardware but help manage code structure, inclusion, and conditional logic during compilation.

Purpose of Compiler Directives:

1. Including Header Files

Used to include external Verilog or definition files, similar to #include in C/C++.

Example:

`include "definitions.v"

2. Defining Macros

Used to define constants or reusable code snippets, often for parameterization or simple text substitution.

Example:

`define WIDTH 8
reg [`WIDTH-1:0] data;

3. Conditional Compilation

Used to compile specific blocks of code only when certain macros are defined, allowing for different configurations or debugging modes.

Example:

`define TEST_MODE
`ifdef TEST_MODE
  initial $display("Test mode enabled");
`endif

4. Undefining Macros

Removes the definition of a previously defined macro.

Example:

`undef WIDTH

5. Error Handling

Used to stop compilation and display a custom error message if a specific condition is met, aiding in design rule checking.

Example:

`error "Invalid configuration detected: WIDTH must be even."

6. Tool-Specific Directives

These are non-standard Verilog directives used to provide hints or instructions to specific synthesis or simulation tools.

Example (common in some tools):

// pragma translate_off
// Simulation-only code
// pragma translate_on

12-bit ECC Word Generation for 8-bit Data

Let’s compute the 12-bit ECC word corresponding to the 8-bit data word '01100001' using Hamming code with parity bits at positions 1, 2, 4, and 8.

Steps for ECC Word Computation:

Step 1: Assign Data Bits to Positions

The 8 data bits (d1 to d8) are placed in the non-parity positions of the 12-bit codeword. The parity bits (p1, p2, p3, p4) are at positions 1, 2, 4, 8.

Data bits: 01100001 (d1=0, d2=1, d3=1, d4=0, d5=0, d6=0, d7=0, d8=1)

Codeword structure (position: bit value):

• 1: p1
• 2: p2
• 3: d1 (0)
• 4: p3
• 5: d2 (1)
• 6: d3 (1)
• 7: d4 (0)
• 8: p4
• 9: d5 (0)
• 10: d6 (0)
• 11: d7 (0)
• 12: d8 (1)

Step 2: Calculate Parity Bits (Even Parity)

Each parity bit is calculated such that the total number of 1s in its group (including the parity bit itself) is even.

• p1 (positions 1, 3, 5, 7, 9, 11):
  Bits: p1, d1(0), d2(1), d4(0), d5(0), d7(0)
p1 ^ 0 ^ 1 ^ 0 ^ 0 ^ 0 = 0 (for even parity)
  p1 ^ 1 = 0 => p1 = 1
• p2 (positions 2, 3, 6, 7, 10, 11):
  Bits: p2, d1(0), d3(1), d4(0), d6(0), d7(0)
p2 ^ 0 ^ 1 ^ 0 ^ 0 ^ 0 = 0
p2 ^ 1 = 0 => p2 = 1
• p3 (positions 4, 5, 6, 7, 12):
  Bits: p3, d2(1), d3(1), d4(0), d8(1)
p3 ^ 1 ^ 1 ^ 0 ^ 1 = 0
p3 ^ 1 = 0 => p3 = 1
• p4 (positions 8, 9, 10, 11, 12):
  Bits: p4, d5(0), d6(0), d7(0), d8(1)
p4 ^ 0 ^ 0 ^ 0 ^ 1 = 0
p4 ^ 1 = 0 => p4 = 1

Step 3: Construct Final 12-bit ECC Word

Substitute the calculated parity bits into their respective positions:

• Position 1: p1 = 1
• Position 2: p2 = 1
• Position 3: d1 = 0
• Position 4: p3 = 1
• Position 5: d2 = 1
• Position 6: d3 = 1
• Position 7: d4 = 0
• Position 8: p4 = 1
• Position 9: d5 = 0
• Position 10: d6 = 0
• Position 11: d7 = 0
• Position 12: d8 = 1

The final 12-bit ECC word is: 110111010001

Verilog Model: Dual-Port 4Kx16-bit SSRAM

This Verilog module implements a dual-port 4Kx16-bit Synchronous Static RAM (SSRAM). One port (Port A) allows both read and write operations, while the other port (Port B) is read-only. Both ports operate synchronously with the rising edge of the clock.

module dual_port_ssram (
    input clk,
    input [11:0] addr_a, addr_b,
    input [15:0] din_a,
    input we_a, re_a, re_b,
    output reg [15:0] dout_a, dout_b
);

    // Declare a 4K (2^12) x 16-bit memory array
    reg [15:0] memory [0:4095];

    // Port A: Read/Write Port
    always @(posedge clk) begin
        if (we_a) begin // Write operation for Port A
            memory[addr_a] <= din_a;
        end
        
        if (re_a) begin // Read operation for Port A
            dout_a <= memory[addr_a];
        end else begin
            // Output high-impedance when not reading
            dout_a <= 16'bz;
        end
    end

    // Port B: Read-Only Port
    always @(posedge clk) begin
        if (re_b) begin // Read operation for Port B
            dout_b <= memory[addr_b];
        end else begin
            // Output high-impedance when not reading
            dout_b <= 16'bz;
        end
    end

endmodule