Understanding the Intel 8086 Microprocessor: Architecture, Addressing Modes, and Interfacing

Intel 8086 System Bus Structure

The Intel 8086 microprocessor utilizes a system bus structure consisting of three primary buses:

  1. Address Bus: This unidirectional bus transmits addresses from the microprocessor to memory or I/O devices.
  2. Data Bus: This bidirectional bus carries data between the microprocessor and memory or I/O devices. The 8086 employs a 16-bit data bus, enabling 16-bit data transfers.
  3. Control Bus: This bus carries control signals that synchronize the microprocessor’s operation with other system components. These signals, including read, write, memory enable, and I/O enable, regulate data and instruction flow between the microprocessor and memory or I/O devices.

DMA Controller

A DMA controller is a specialized peripheral device that facilitates data transfers between external devices and memory without direct microprocessor involvement. Here’s a breakdown of the DMA process:

  1. Initialization: The microprocessor configures the DMA controller by specifying parameters like source and destination addresses, transfer size, and transfer mode.
  2. Request: When an external device, such as a disk drive or network interface, needs to transfer data to or from memory, it initiates a request to the DMA controller.
  3. Arbitration: In scenarios with multiple devices requesting DMA access concurrently, the DMA controller employs arbitration to prioritize access, ensuring equitable memory bus utilization.
  4. Bus Mastering: Upon gaining access, the DMA controller assumes the role of bus master, taking control of the system bus. This enables direct data transfers between memory and the requesting device, bypassing the microprocessor.
  5. Transfer: The DMA controller executes the data transfer between the external device and memory using the microprocessor-defined addresses and parameters. This independent handling of data transfer frees the microprocessor for other tasks.
  6. Completion: Upon transfer completion, the DMA controller may issue an interrupt to signal the microprocessor.

The DMA controller significantly enhances system performance by offloading data transfer tasks from the microprocessor, allowing it to focus on instruction execution and higher-level computations.

Intel 8086 Addressing Modes

The Intel 8086 microprocessor supports various addressing modes, dictating how operands are accessed in memory or registers. Here are some common examples:

  1. Immediate Addressing Mode: The operand is directly embedded within the instruction.
    Example: MOV AX, 1234h
  2. Register Addressing Mode: The operand resides within a register.
    Example: MOV AX, BX
  3. Direct Addressing Mode: The instruction explicitly specifies the memory address where the operand is located.
    Example: MOV AX, [1234h]
  4. Register Indirect Addressing Mode: The operand’s memory address is stored within a register.
    Example: MOV AX, [BX]
  5. Indexed Addressing Mode: The operand’s memory address is calculated by adding a displacement to the contents of a base register.
    Example: MOV AX, [BX+SI]
  6. Based Addressing Mode: The operand’s memory address is determined by adding a displacement to the contents of a base register.
    Example: MOV AX, [BX+1234h]
  7. Based Indexed Addressing Mode: The operand’s memory address is computed by adding a displacement to the sum of the contents of a base register and an index register.
    Example: MOV AX, [BX+SI+1234h]

String Instructions in Intel 8086

String instructions are employed to manipulate strings of data stored in memory. They typically operate on data blocks identified by a starting address (ESI for source, EDI for destination) and a count (ECX).

    • Function: Transfer a byte/word/doubleword from the memory location pointed to by ESI to the memory location pointed to by EDI.
    • Opcode: MOVSB (A4), MOVSW (A5), MOVSD (A5 for 32-bit mode)
    • Function: Compare a byte/word/doubleword at the memory location addressed by ESI with the corresponding data at the memory location addressed by EDI.
    • Opcode: CMPSB (A6), CMPSW (A7), CMPSD (A7 for 32-bit mode)
    • Function: Compare a byte/word/doubleword at the memory location addressed by EDI with the byte/word/doubleword stored in the AL/AX/EAX register.
    • Opcode: SCASB (AE), SCASW (AF), SCASD (AF for 32-bit mode)
    • Function: Load a byte/word/doubleword from the memory location addressed by ESI into the AL/AX/EAX register.
    • Opcode: LODSB (AC), LODSW (AD), LODSD (AD for 32-bit mode)
    • Function: Store the byte/word/doubleword contained in the AL/AX/EAX register at the memory location addressed by EDI.
    • Opcode: STOSB (AA), STOSW (AB), STOSD (AB for 32-bit mode)
    • Function: Repeat the subsequent string instruction indicated by the mnemonic until the ECX register reaches zero or a specified condition is met.
    • Opcode: F3 (REP/REPE/REPZ), F2 (REPNE/REPNZ)

Common Assembler Directives in 8086 Programming

Assembler directives provide instructions to the assembler itself, rather than the CPU. They facilitate tasks such as data definition, memory allocation, and assembly process control.

  1. DB (Define Byte):
    • Syntax: label DB value1 [, value2, ...]
    • Function: Defines one or more byte-sized data elements.
  2. DW (Define Word):
    • Syntax: label DW value1 [, value2, ...]
    • Function: Defines one or more word-sized data elements.
  3. DD (Define Doubleword):
    • Syntax: label DD value1 [, value2, ...]
    • Function: Defines one or more doubleword-sized data elements.
  4. DS (Data Segment):
    • Syntax: DS segment
    • Function: Designates a segment for data storage.
  5. CS (Code Segment):
    • Syntax: CS segment
    • Function: Defines a segment for code storage.
  6. SS (Stack Segment):
    • Syntax: SS segment
    • Function: Specifies a segment to be used as the stack.
  7. ES (Extra Segment):
    • Syntax: ES segment
    • Function: Defines an auxiliary segment for supplementary data storage.
  8. ORG (Origin):
    • Syntax: ORG address
    • Function: Sets the starting address for the program or data.
  9. END (End):
    • Syntax: END label
    • Function: Marks the program’s termination point.
  10. EQU (Equation):
    • Syntax: label EQU value
    • Function: Assigns a constant value to a label.
    • Function: Defines a segment and indicates its end.
  12. PROC/ENDP:
    • Function: Defines a procedure and marks its end.

Programmable Interrupt Controller (PIC)

In computing, PIC stands for”Programmable Interrupt Controller” This peripheral device manages interrupts within a computer system. The PIC receives interrupt requests from various hardware devices, prioritizes them, and then forwards them to the CPU for processing.

Key functions of a PIC include:

  1. Interrupt Prioritization: The PIC categorizes interrupt requests based on their priority levels, ensuring that higher-priority interrupts are serviced before lower-priority ones.
  2. Interrupt Masking: The PIC enables the CPU to selectively enable or disable specific interrupts, aiding in system resource management and preventing interruptions during critical operations.
  3. Interrupt Vectoring: Upon interrupt occurrence, the PIC provides the CPU with an interrupt vector, which is a memory address pointing to the corresponding interrupt service routine (ISR).
  4. Interrupt Acknowledgment: The PIC communicates with the CPU to acknowledge the receipt and processing of an interrupt request.

Interfacing a Stepper Motor with the 8051 Microcontroller

Interfacing a stepper motor with the 8051 microcontroller involves controlling the motor’s movement by sending precise signals to its coils. Here’s a general overview:

  1. Driver Circuit: Stepper motors demand higher current and voltage levels than a microcontroller can directly supply. A driver circuit amplifies the microcontroller’s signals to drive the stepper motor coils. Commonly used driver ICs include ULN2003 or L293D.
  2. Connections: Connect the stepper motor to the driver circuit. Stepper motors typically have four or more wires, each corresponding to a coil. The driver circuit provides the necessary power to these coils.
  3. Programming: Develop a program in assembly or C language to control the stepper motor. The program should generate the appropriate signal sequence for the motor coils to achieve the desired direction and number of steps.
  4. Sequence Control: Stepper motors move in discrete steps, and the signal sequence sent to the coils determines the direction and step size. Full Step and Half Step sequences are the most prevalent.
  5. Timing: Stepper motors have a maximum speed for reliable stepping. Precisely control the timing between steps to ensure smooth and accurate movement.
  6. Feedback (Optional): Incorporate feedback mechanisms like limit switches or encoders to provide information about the motor’s position or movement.

8051 Microprocessor Architecture

The 8051 microprocessor follows the Harvard architecture and features:

  • 4-byte internal data RAM
  • 128 bytes of special function registers
  • 8-bit data bus and 16-bit address bus
  • 4 register banks
  • Timers
  • I/O ports for interfacing with external devices

The 8051 has four I/O ports (P0, P1, P2, P3), each with 32 I/O pins configurable as input or output for interfacing with external devices.

Interfacing a Stepper Motor with the 8051 Microprocessor

  1. Connect the stepper motor to a driver IC.
  2. Connect the driver IC to the 8051 microprocessor.
  3. Write the control signals in your program.
  4. Program the 8051 microprocessor.
  5. Execute the program.