Understanding CPU Registers, Instructions, and Addressing Modes

Posted on Oct 4, 2025 in Computers

CPU Registers and Architecture Fundamentals

General Purpose Registers (GPRs)

These 16-bit registers are typically used for arithmetic and data manipulation:

  • AX (Accumulator): Used for main arithmetic operations, disk I/O, multiplication and division instructions, and decimal corrections.
  • BX (Base): Serves as the base register for memory addresses referenced indirectly.
  • CX (Counter): Primarily used as a counter in loops and repetitive string operations.
  • DX (Data): Used in conjunction with AX during multiplication and division operations.

Pointer and Index Registers

These registers manage memory access, especially for the stack and data arrays:

  • SP (Stack Pointer): Points to the top of the stack. Used by stack operating instructions (PUSH/POP).
  • BP (Base Pointer): A pointer to an area within the stack frame that stores data.
  • SI (Source Index): Index register used for indirect addressing in certain modes. Often serves as the source pointer in string operations.
  • DI (Destination Index): Index register that serves as the destination pointer for string operations.

Segment Registers and Instruction Pointer

  • Segment Registers: CS, DS, ES, FS, GS, SS. These registers define the starting addresses of memory segments (Code, Data, Extra, Stack).
  • IP (Instruction Pointer): Holds the offset address of the next instruction to be executed within the code segment. It is automatically modified when an instruction is read.

Flags Register (Program Status Word – PSW)

The PSW (Program Status Word) contains status bits that the CPU uses to track conditions. These bits are adjusted by the ALU after each operation, reflecting the most recent state of the computation.

Condition Flags (Bits)

  • N (Negative): Set if the result was negative.
  • Z (Zero): Set if the result was zero.
  • V (Overflow): Set if the result caused an overflow.
  • C (Carry): Set if the result caused a carry out of the leftmost bit.
  • A (Auxiliary Carry): Set if there was a carry from bit 3 (used for BCD arithmetic).
  • P (Parity): Set if the result had even parity.

CPU Instruction Set Architecture

Instruction Formats

While instruction formats vary widely, the most commonly used structures include:

  • Opcode only (Cod.Op)
  • Opcode and one direct address (Cod.Op-Dir)
  • Opcode, Destination, Source (Cod.Op, Dir1, Dir2)
  • And other variations.

Categories of CPU Instructions

Instructions for any CPU generally fall into the following categories:

  1. Data Transfer Instructions
  2. Arithmetic Instructions
  3. Logic Instructions
  4. Flow Control Instructions
  5. Input / Output Instructions

1. Data Transfer Instructions

These instructions move data from one location to another. If memory is involved, the instruction determines the memory address and performs the read/write operation.

  • MOVE: Transfers data between registers in the CPU.
  • STORE: Transfers data from a register to memory (Register → Memory).
  • LOAD: Transfers data from memory to a register (Memory → Register).
  • CLEAR: Sets a register value to zero.
  • SET: Sets a register value to one.
  • PUSH: Enters data onto the stack.
  • POP: Removes data from the stack.

2. Arithmetic Instructions

These instructions perform operations in the ALU, often involving data transfers before and/or after the operation. They update condition codes and indicators (flags).

  • ADD: Adds two operands.
  • SUBTRACT: Subtracts two operands.
  • MULTIPLY: Multiplies two operands.
  • DIVIDE: Divides two operands.
  • ABSOLUTE: Calculates the absolute value of the operand.
  • NEGATIVE: Changes the sign of the operand.
  • INCREMENT: Increases the operand by 1.
  • DECREMENT: Decreases the operand by 1.

3. Logic Instructions

  • AND: Performs bitwise logical AND.
  • OR: Performs bitwise logical OR.
  • NOT: Performs bitwise logical NOT.
  • XOR: Performs bitwise exclusive OR.
  • TEST: Evaluates conditions (often setting flags without storing a result).
  • COMPARE: Compares two operands (setting flags based on the difference).
  • SHIFT: Scrolls bits left or right.
  • ROTATE: Performs cyclic displacement (rotation) of bits.

4. Flow Control Instructions

  • JUMP (Unconditional): Transfers execution to a new address unconditionally.
  • JUMP TO (Conditional): Transfers execution based on a condition (e.g., flag status).
  • JUMP SUB (Subroutine Jump): Jumps to a subroutine, saving the return address.
  • RETURN: Returns from a subroutine.
  • SKIP: Increases the Program Counter (PC) by 1, skipping the next instruction.
  • SKIP TO (Conditional): Increases the PC by 1 conditionally.
  • HALT: Stops program execution.
  • WAIT: Pauses execution until a specific condition is met.
  • NOP (No Operation): Executes no operation.

5. Input / Output Instructions

  • INPUT: Transfers data from I/O device to memory or a register.
  • OUTPUT: Transfers data from memory or a register to an I/O device.
  • START I/O: Initializes an I/O device.
  • TEST I/O: Transfers status information from an I/O device.

CPU Addressing Modes

Addressing modes define how the operand address is calculated during instruction execution.

Immediate Addressing

The operand value is contained directly within the instruction itself. This is fast because no memory reference is needed.

Example: MOV AX, 10 (The value 10 is copied to AX).

Note: Immediate addressing is typically restricted and cannot be used with Segment Registers (CS, DS, ES, SS) or the Instruction Pointer (IP).

Direct Addressing

The instruction specifies the exact memory address (N) where the operand is located.

Example: ADD (941) (The operand is at memory address 941).

This requires only one memory access to retrieve the operand.

Indirect Addressing

The instruction specifies an address (N) that contains the address of the operand.

  • Operand = ((N))
  • This mode is slower due to multiple memory accesses required to find the final operand.

Register Addressing

The operand is located entirely within a CPU register specified by the instruction.

  • This is the fastest addressing mode.
  • No memory access is required.
  • The address space is restricted to the available CPU registers.

Register Indirect Addressing

The instruction specifies a register (Reg) that holds the memory address of the operand.

  • The register acts as a pointer to the operand in memory.
  • This requires one memory access (less than pure indirect addressing).