Understanding Computer Architecture: Buses, Addressing, and Memory
Computer Bus Architecture
Bus: In computer architecture, a bus is a transport mechanism that logically connects several peripherals using the same set of wires. This concept is similar to a shuttle, facilitating internal data transfers within a computer system during operation.
A bus is defined as a set of electrical connectors, typically metal tracks printed on the motherboard, through which signals travel. These signals correspond to the binary machine language used by the microprocessor.
The main function of a bus is to perform data transfer between different computer units. The unit initiating and controlling the transfer is known as the master, while the unit on which the transfer takes place is the slave. These roles are dynamic, allowing a unit to function as both master and slave in different transfers.
Basic information transfer using the master involves two main groups of lines:
- Directional Lines: Determines the unit involved in the transfer.
- Data Lines: Carries the data being transferred.
Control Lines: Dictate the transfer operation to be performed by the data and address lines, marking the temporal ordering of signals on the bus. Key control lines include:
- Memory write
- Memory read
- Memory operation
- Input operation
Synchronization lines include transfer acknowledgment, clock, and reset signals.
Arbitration lines manage bus access requests based on priority, including:
- Bus request
- Bus selection
- Bus arbitration occupation
- Addresses
- Control data
- CPU
- Memory
- I/O
Bus lines are classified by directionality as:
- Unidirectional lines (simple transmitter and multiple)
- Bidirectional lines
Standard Buses
Local Bus: A bus located between the CPU, memory, and peripheral devices. The CPU accesses its chips internally via a 32-bit access, configurable in three forms: single target, multiple electrical, and multiple initiator.
Bus Standard: A set of lines on a metal elective printed circuit board. Standardized bus levels include mechanical, electrical, logical, synchronization, and arbitration aspects.
Bus I/O: Responsible for data input and output of the entire system, connecting through adapters in a processor memory bus.
The Data Bus is subdivided into three buses:
- Address Bus
- Control Bus
- Data Bus
The Address Bus indicates the memory location or device to connect to. The Control Bus sends arbitration signals between devices. The Data Bus transmits the bits, typically with a power of approximately 2.
Address Bus
The Address Bus is a set of power lines needed to establish an address on a separate channel from the microprocessor’s data bus.
Memory Addresses
Memory addressing can be viewed from two perspectives: physical and logical.
- Physical: Relates to the electronic media used to access different memory locations.
- Logical: The way addresses are expressed and maintained.
Real Mode
Real Mode: An operating mode supported by 80286 and later CPUs in the x86 architecture. Real mode is characterized by a 20-bit segmented address space, allowing it to address only 1MB of memory. It provides direct access to BIOS software routines and hardware peripherals and lacks memory protection or multitasking at the hardware level.