Understanding 8085 and 8086 Microprocessors: Architecture, Addressing Modes, and Evolution
8085 Addressing Modes
Addressing modes define how operands are specified in instructions. The 8085 microprocessor utilizes the following addressing modes:
1. Immediate Addressing Mode
Data is embedded directly within the instruction. Instructions with ‘I’ in their mnemonics often use this mode.
Examples: MVI A, 05H; ADI 55H; LXI H, C000H
2. Register Addressing Mode
Data resides in a register, and the instruction references that register.
Examples: MOV A, B; ADD B; ANA C
3. Direct Addressing Mode
The instruction specifies the memory address of the data. This allows for separate storage of instructions and data.
Examples: LDA 2000H; STA 2000H; IN 10H; OUT 01H
4. Register Indirect Addressing Mode
The instruction points to a register pair that holds the address of the data.
Examples: LDAX B; STAX D; MOV M, A
5. Implied Addressing Mode
The opcode itself implies the operand.
Examples: RAL; RRC
Bus Structure of a Microprocessor
A bus is a communication pathway (a set of wires or lines) that carries data, addresses, and control signals.
1. Address Bus
The CPU uses the address bus to specify the memory location to read from or write to. It’s unidirectional, meaning data flows only from the microprocessor to peripherals. The number of address lines (N) determines the addressable memory locations (2^N). The 8085, with its 16-bit address bus, can access up to 64 KB of memory (2^16 = 65536 bytes).
2. Data Bus
The 8085’s 8-bit data bus carries data (00000000H to 11111111H) between the CPU, memory, and I/O ports. It’s bidirectional, allowing data flow in both directions.
3. Control Bus
The control bus carries signals from the CPU to manage and synchronize operations with memory and I/O devices.
Control signals include:
- Memory read
- Memory write
- I/O read
- I/O write
8085 Internal Architecture
Arithmetic and Logic Unit (ALU)
The ALU performs arithmetic and logical operations. It includes:
- Accumulator: An 8-bit general-purpose register connected to the ALU, frequently used in operations.
- Temporary Register: Not user-accessible, used internally by the ALU for calculations.
- Flag Register: An 8-bit register with five flip-flops indicating the status of operations (Sign, Zero, Auxiliary Carry, Carry, Parity).
Register Array
- Temporary Registers (W, Z): Not user-accessible, used internally during operations.
- General Purpose Registers (B, C, D, E, H, L): Six 8-bit registers for data manipulation, usable individually or as 16-bit pairs (BC, DE, HL).
- Special Purpose Registers:
- Stack Pointer (SP): A 16-bit register holding the address of the stack (used for PUSH and POP operations).
- Program Counter (PC): A 16-bit register holding the address of the next instruction. It increments automatically after instruction execution.
Timing and Control Unit
Synchronizes operations with the clock and generates control signals for communication between the microprocessor and peripherals.
Instruction Register and Decoder
The Instruction Register holds the fetched instruction, and the Decoder interprets it to determine the sequence of operations.
Interrupt Control
Handles interrupts such as TRAP, RST 5.5, RST 6.5, RST 7.5, and INTR. INTA acknowledges interrupt requests.
Serial I/O Control
Manages serial data transmission and reception using SID (Serial Input Data) and SOD (Serial Output Data) signals, controlled by SIM and RIM instructions.
Evolution of Intel Microprocessors
16-bit Microprocessors
- 8086 (1978): Intel’s first 16-bit microprocessor, with a 20-bit address bus (1 MB memory access) and a clock speed of 5-10 MHz.
- 8088 (1979): A cost-effective variant of the 8086 with an 8-bit data bus, famously used in the IBM PC.
- 80286 (1982): A 16-bit microprocessor with a 24-bit address bus (16 MB memory access) and a clock speed of 8 MHz.
32-bit Microprocessors
- 80386 (1986): Intel’s first 32-bit microprocessor, with a 32-bit address bus (4 GB memory access) and clock speeds ranging from 16 MHz to 33 MHz.
- 80486 (1989): A 32-bit microprocessor with clock speeds from 16 MHz to 100 MHz, introducing an 8 KB on-chip cache.
- Pentium (1993): A 32-bit microprocessor with a 66 MHz clock speed, featuring separate 8 KB instruction and data caches.
- Pentium II (1997): A 32-bit microprocessor with clock speeds from 233 MHz to 450 MHz, introducing MMX technology and integrating the L2 cache.
- Pentium III (1999): A 32-bit microprocessor with clock speeds from 500 MHz to 1.4 GHz.
- Pentium IV (2000): A 32-bit microprocessor with clock speeds from 1.3 GHz to 3.8 GHz, featuring a 32 KB L1 cache and a 256 KB L2 cache.
- Intel Dual Core (2006): A 32-bit/64-bit microprocessor with two cores, each having its own L1 cache but sharing the L2 cache and external bus.
64-bit Microprocessors
- Intel Core 2 (2006): A 64-bit microprocessor with clock speeds from 1.2 GHz to 3 GHz, available in Duo, Quad, and Extreme versions.
- Intel Core i7 (2008): A 64-bit microprocessor with four cores, clock speeds from 2.66 GHz to 3.33 GHz, and a three-level cache hierarchy (L1, L2, L3).
- Intel Core i5 (2009): A 64-bit microprocessor with four cores, clock speeds from 2.40 GHz to 3.60 GHz, and a three-level cache hierarchy.
- Intel Core i3 (2010): A 64-bit microprocessor with two cores, clock speeds from 2.93 GHz to 3.33 GHz, and a three-level cache hierarchy.
- Intel Core i9 (2017): A 64-bit microprocessor with up to 10 cores, clock speeds from 3.3 GHz to 4.5 GHz, and a large L3 smart cache.
8086 Addressing Modes
The 8086 microprocessor expanded upon the addressing modes of its predecessors:
1. Register Addressing Mode
An 8-bit or 16-bit general-purpose register holds the operand.
Examples: MOV BX, CX; ADD CX, DX
2. Immediate Addressing Mode
The operand is directly specified within the instruction.
Examples: MOV AL, 58h; MOV BX, 0340h
3. Direct Addressing Mode
The instruction contains the effective address (offset) of the operand in memory.
Examples: MOV AL, [0300h]; MOV [0401h], AX
4. Register Indirect Addressing Mode
The operand’s offset is stored in a base register (BX, BP, SI, or DI).
Examples: ADD CX, [BX]; MOV DX, [SI]
5. Based Addressing Mode
The operand’s offset is calculated by adding a displacement (8-bit or 16-bit) to the contents of a base register (BX or BP).
Example: ADD AL, [BX + 04h]
6. Indexed Addressing Mode
The operand’s offset is calculated by adding a displacement (8-bit or 16-bit) to the contents of an index register (SI or DI).
Examples: ADD AX, [SI + 08h]; MOV CX, [SI + 1234h]
7. Based Indexed Addressing Mode
The operand’s offset is calculated by adding the contents of a base register (BX or BP) to the contents of an index register (SI or DI).
Example: MOV A, [BX + SI]; ADD CX, [BX + SI]
Note: BX is used as the base register for the data segment (DS), while BP is used for the stack segment (SS).