Semiconductor Fabrication Fundamentals: Materials and Processes
Most Important Semiconductor Material
The most important semiconductor material is Silicon (Si).
Reasons:
- Abundant and inexpensive
- Forms high-quality SiO₂ oxide layer (essential for MOSFETs)
- Good electrical properties (bandgap = 1.12 eV)
- High thermal stability
- Easy to purify and grow as single crystal
Nanofabrication and Die Definition
Nanofabrication is the process of designing and manufacturing devices and structures with dimensions in the nanometer range (1–100 nm) using techniques like photolithography, etching, and deposition.
A die is a single individual chip cut from a semiconductor wafer that contains an integrated circuit.
Predominant Device in Electronics
The most commonly used device is the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), especially in CMOS technology.
Advantages:
- Very low power consumption
- Allows very high integration density
- Produces less heat
- High switching speed
- Used in processors, memory, and mobile chips
Silicon Purity Expression (9N)
Purity expressed as 9N means 99.9999999% pure silicon.
Explanation:
Each “N” represents a 9 in purity percentage.
Importance:
High purity is required to ensure proper electrical behavior and fewer defects in semiconductor devices.
Moore’s Law Explanation
The number of transistors on an integrated circuit doubles approximately every 18–24 months, while cost per transistor decreases.
Consequences:
- Leads to: Higher performance, Smaller device size, Lower cost, Higher computing power
Proposed by Gordon Moore (1965).
FEOL, BEOL, and MEOL Definitions
FEOL (Front End Of Line)
Definition: FEOL is the fabrication stage where transistors and active devices are formed on the silicon wafer.
Includes: Oxidation, Doping, Gate formation, Source and drain creation
Focus: Device formation
BEOL (Back End Of Line)
Definition: BEOL is the stage where metal interconnections are formed to connect transistors.
Includes: Metal deposition, Interconnect formation, Passivation
Focus: Electrical connections
MEOL (Middle End Of Line)
Definition: MEOL is the intermediate stage between FEOL and BEOL involving contact formation between transistor and metal layers.
Includes: Contact formation, Silicide formation, Local interconnects
When introduced: MEOL became important in modern CMOS (around 90 nm and below) technology nodes.
Via in CMOS
Definition: A via is a small vertical hole filled with metal that connects one metal layer to another.
Function: Provides vertical electrical connection between interconnect layers.
Silicon Wafer, Doping, and Fabrication Introduction
Wafer Definition and Standard Size
A wafer is a thin circular slice of semiconductor material (usually silicon) used as the base for IC fabrication.
Standard sizes:
- 100 mm (4 inch)
- 150 mm (6 inch)
- 200 mm (8 inch)
- 300 mm (12 inch) most common today
Doping Process and Purpose
Doping is the process of adding impurity atoms to silicon.
Methods:
- Ion implantation
- Diffusion
Types:
- n-type → Phosphorus, Arsenic
- p-type → Boron
Why doping is done:
- To control electrical conductivity
- To form PN junctions
- To create transistors
Semiconductor Fabrication Introduction
Semiconductor fabrication is the process of manufacturing integrated circuits (ICs) and electronic devices on a silicon wafer using a sequence of chemical and physical processes in a highly controlled cleanroom environment. The goal is to create millions or billions of transistors and interconnections on a single chip.
Main steps involved:
- Wafer preparation: Pure silicon crystal is grown (Czochralski method), sliced into thin wafers, and polished to obtain a smooth surface.
- Oxidation: A thin layer of silicon dioxide (SiO₂) is formed on the wafer to act as an insulating layer.
- Photolithography: Circuit patterns are transferred onto the wafer using UV light and photoresist.
- Doping: Impurity atoms (boron or phosphorus) are introduced by diffusion or ion implantation to control electrical properties.
- Deposition and Etching: Thin films of materials are deposited and unwanted material is removed to form device structures.
- Metallization and Packaging: Metal layers are added to create electrical connections, then the wafer is cut into dies, tested, and packaged.
Conclusion: Semiconductor fabrication enables the production of microprocessors, memory chips, and electronic components, forming the foundation of modern electronics such as computers, smartphones, and sensors.
Key Fabrication Terms
Wafer
A wafer is a thin circular slice of semiconductor material (usually silicon) used as the base for IC fabrication. Many identical chips (dies) are fabricated on one wafer.
Nanostructure
A nanostructure is a structure with dimensions in the nanometer range (1–100 nm), such as modern transistor gates and interconnects. These enable high-density and high-speed devices.
Scaling & Moore’s Law
Scaling: Reducing transistor size to increase density and performance while reducing power consumption.
Moore’s Law: The number of transistors on a chip doubles every 18–24 months, increasing computing power and reducing cost per transistor.
Use of Oxidation
Oxidation is the process of forming a silicon dioxide (SiO₂) layer on silicon.
Uses:
- Insulator layer
- Gate oxide in MOSFET
- Protective layer
- Mask during doping
Silicon in Nanofabrication
Silicon is the most widely used semiconductor because:
- Forms stable SiO₂
- Has suitable bandgap (1.12 eV)
- Abundant and low cost
- High thermal stability
Different Types of Silicon (in fabrication context)
Common types include:
- n-type silicon: Doped with phosphorus or arsenic
- p-type silicon: Doped with boron
- Single crystal silicon: Used in IC fabrication
- Polycrystalline silicon: Used for gates and solar cells
Purity
Semiconductor silicon must be extremely pure, called Electronic Grade Silicon (EGS).
Example:
9N purity = 99.9999999% pure
High purity ensures proper electrical performance and fewer defects.
Defects
Defects are imperfections in the crystal structure that affect device performance.
Types:
- Point defects (vacancies, impurities)
- Dislocations
- Surface defects
Effects:
- Reduce device efficiency
- Cause leakage currents
CMOS Fabrication Steps Summary
CMOS Fabrication Steps
CMOS fabrication is used to make integrated circuits.
Main steps:
Wafer preparation, Oxidation, Photolithography, Doping, Deposition, Etching, Metallization, Packaging
Masks
A mask is a patterned plate used in photolithography to transfer circuit patterns onto the wafer using UV light. Each layer of the chip requires a separate mask.
FEOL (Front End Of Line)
Stage where transistors are formed on the silicon wafer.
Includes: Oxidation, Doping, Gate formation, Source and drain formation
MEOL (Middle End Of Line)
Stage between FEOL and BEOL where contacts between transistor and metal layers are formed.
Includes: Contact formation, Silicide formation
BEOL (Back End Of Line)
Stage where metal interconnections are created to connect transistors.
Includes: Metal deposition, Via formation, Interconnect layers
Fabrication of Crystal Silicon
Steps:
- Silicon extracted from sand → Metallurgical Grade Silicon (MGS)
- Purified to Electronic Grade Silicon (EGS)
- Single crystal grown (Czochralski process)
- Sliced into wafers and polished
MGS (Metallurgical Grade Silicon)
Purity: about 98–99%
Produced from quartz in furnace
Used as raw material for further purification
EGS (Electronic Grade Silicon)
Purity: 99.9999999% (9N)
Used in semiconductor device fabrication
Produced by chemical purification of MGS
Etching
Etching removes unwanted material from wafer
Types:
- 1. Wet etching: Uses liquid chemicals; Simple but less precise
- 2. Dry etching: Uses gases or plasma; More precise
- 3. Plasma etching: Ionized gas removes material; Used in nanometer fabrication
- 4. Sputter etching: High-energy ions knock atoms off surface
Advanced Process Details
CMOS Fabrication Steps for Well Creation (Twin Tub Process)
Answer:
Start with a lightly doped substrate.
Grow an oxide layer and deposit nitride.
Pattern the n-well using lithography and implant donors (e.g., Phosphorus).
Grow thick oxide over the n-well regions.
Remove nitride and implant acceptors (e.g., Boron) for the p-well (self-aligned to the n-well oxide).
Drive-in (anneal) to diffuse the dopants deep into the substrate to form the wells.
Czochralski (CZ) vs. Float Zone (FZ) Growth Methods
Answer:
- Purity: FZ is purer (no crucible contact), while CZ has higher Oxygen content.
- Cost: CZ is cheaper; FZ is expensive.
- Size: CZ produces large wafers (up to 450mm); FZ is limited to smaller diameters.
- Application: CZ is used for generic CMOS/Logic; FZ is used for high-voltage power devices due to its high resistivity.
Photoresist Definition
Answer: A light-sensitive organic polymer material used to transfer a pattern from a mask onto a wafer.
Positive vs. Negative Photoresist
Answer:
- Positive: Exposed areas become soluble and are washed away.
- Negative: Exposed areas become cross-linked (hard) and remain; unexposed areas wash away.