Semiconductor Devices: Fundamentals of Doping, Transistors, and Rectification

Posted on Oct 4, 2025 in Technology

Doped Semiconductors and Energy Band Theory

Why Impure Semiconductors (Doping) Are Necessary

• Pure (intrinsic) Si/Ge have very low conductivity at room temperature.
• Doping adds controlled carriers, leading to practical conductivity and device action.
• n-type (Donors, 5 valence e⁻): Impurities like P, As, Sb create majority electrons.
• p-type (Acceptors, 3 valence e⁻): Impurities like B, Ga, In create majority holes.
• Doping is used to engineer essential devices like diodes, BJTs, JFETs, MOSFETs, and resistors.

Energy Band Diagrams

• Conductor: Valence and conduction bands overlap (Bandgap $E_g \approx 0$).
• Semiconductor (e.g., Si $E_g \approx 1.1 \text{ eV}$): Small bandgap allows some carriers to exist at $300 \text{ K}$.
• Insulator ($E_g > \sim 5 \text{ eV}$): Large gap results in negligible carriers.

Conductor           Semiconductor           Insulator
| Valence |         | Valence |             | Valence  |
| Band    |         | Band    |             | Band     |
|_________|         |_________|             |__________|
Overlap             Gap (~1 eV)             Large Gap (>3 eV)
| Conduction Band | | Conduction Band |   | Conduction Band |

BJT and FET Transistors: Control Mechanisms and Differences

Current Control vs. Voltage Control

• BJT (Bipolar Junction Transistor): $I_C \approx \beta I_B$. A base current ($I_B$) is required to forward bias the base–emitter junction. The output current is controlled by the input current, making it current-controlled.
• FET (Field-Effect Transistor): The gate is reverse-biased or insulated, resulting in negligible gate current. The channel charge (and thus $I_D$) is set by the gate-source voltage ($V_{GS}$), making it voltage-controlled.
• Input Resistance: BJT (k$\Omega$–tens k$\Omega$) vs. FET (M$\Omega$–G$\Omega$).

Semiconductor Device Symbols

NPN BJT:           n-JFET:                  n-MOSFET (Enh.)
   C                 D                       D
   |                 |                       |
 B ─┤▶├─ E         G ─┤─── S                 G ─┤ │─ S
   |                 |                       |

Comparison of BJT and FET Features

NPN BJT Operation and Base Width Modulation

Working Principle of NPN BJT (Active Mode)

An NPN transistor works in active mode when:

• Base-Emitter Junction (BEJ) is Forward Biased.
• Base-Collector Junction (BCJ) is Reverse Biased.

Step-by-Step Working:

1. Biasing: A small voltage $V_{BE} \approx 0.7 \text{ V}$ is applied between the base and emitter. A higher voltage $V_{CE}$ is applied between the collector and emitter.

2. Carrier Injection: The emitter is heavily doped and injects electrons (majority carriers) into the base.

   • The base is lightly doped and very thin, so only a small portion of electrons recombine with holes there.

3. Collector Action: Most electrons are swept into the collector due to the reverse bias field. A large collector current ($I_C$) flows, proportional to the base current ($I_B$).

Simplified NPN BJT Diagram:

Emitter (arrow) ----|\
                   | >---- Base
Collector ---------|/

Early Effect in BJT (Base Width Modulation)

• The Early effect occurs when the collector-base voltage ($V_{CB}$) increases.
• This increase widens the collector-base depletion region, which consequently reduces the effective base width.
• Due to the narrower base, fewer electrons recombine in the base, causing the collector current ($I_C$) to increase slightly, even if the base current ($I_B$) is constant.
• It causes non-ideal transistor behavior:
  • Slight increase in $I_C$ with $V_{CE}$.
  • Reduced output resistance.
  • Variation in current gain ($\beta$).

JFET and Enhancement MOSFET Characteristics

n-Channel JFET Drain Characteristics

• Graph: Drain current ($I_D$) vs. Drain-Source voltage ($V_{DS}$) for different Gate-Source voltages ($V_{GS}$).
• Regions:
  • Ohmic Region: At low $V_{DS}$, $I_D$ increases linearly.
  • Saturation (Pinch-off) Region: $I_D$ becomes approximately constant.
  • Cut-off Region: When $V_{GS} \le V_P$ (Pinch-off Voltage), $I_D = 0$.

n-Channel Enhancement MOSFET Structure and Working

Structure

• Built on a lightly doped p-type substrate.
• Two heavily doped $n^+$ regions form the Source (S) and Drain (D).
• A thin insulating layer of silicon dioxide ($ ext{SiO}_2$) is placed between the Gate (G) and the substrate.
• The gate terminal is metallic and insulated, meaning no direct current flows into the gate.
• The substrate/body is usually connected to the source terminal.
• No physical n-channel exists initially; the channel is “enhanced” by applying gate voltage.

Working Principle

1. At $V_{GS} = 0 \text{ V}$: No conduction occurs between the drain and source because the p-type body prevents current flow (no channel is formed).

2. When $V_{GS} > V_{th}$ (Threshold Voltage): A positive voltage applied at the gate attracts electrons towards the $ ext{SiO}_2$ interface. Electrons accumulate near the surface, forming an inversion layer (n-channel).

3. This allows current ($I_D$) to flow from drain $\rightarrow$ source when $V_{DS} > 0$. As $V_{GS}$ increases beyond $V_{th}$, channel width increases, and drain current $I_D$ increases approximately quadratically in the saturation region.

PN Junction Diodes and AC-to-DC Conversion

PN Junction Fundamentals: Depletion Region and Barrier Potential

• Depletion Region: This is the area around the PN junction where mobile charge carriers (free electrons and holes) are depleted. When the junction forms, carriers diffuse and recombine, leaving behind fixed charged ions (positive donors in the n-region and negative acceptors in the p-region). This region is devoid of free carriers and is also called the space charge region.
• Barrier Potential (Built-in Potential): Due to the fixed charged ions, an electric field is established across the depletion region. This field creates a potential difference called the barrier potential or built-in voltage ($V_{bi}$), which opposes further diffusion of carriers. This potential must be overcome by an external voltage for the diode to conduct current.

Depletion Width Calculation Example (Silicon Diode)

Calculation Parameters:

• Donor Concentration ($N_D$): $10^{20} \text{ cm}^{-3}$
• Acceptor Concentration ($N_A$): $10^{16} \text{ cm}^{-3}$
• Intrinsic Carrier Concentration ($n_i$): $10^{10} \text{ cm}^{-3}$
• Thermal Voltage ($V_T = kT/q$): $\approx 0.02585 \text{ V}$ (at $300 \text{ K}$)

1. Built-in Potential ($V_{bi}$)

Formula: $V_{bi} = V_T \cdot \ln\left( \frac{N_A \cdot N_D}{n_i^2} \right)$

Vbi = 0.02585 * ln( (10^16 * 10^20) / (10^10)^2 )
Vbi = 0.02585 * ln(10^16)
Vbi \approx 0.95 V

2. Total Depletion Width ($W$)

Formula: $W = \sqrt{ \frac{2 \cdot \epsilon_s}{q} \cdot \left( \frac{N_A + N_D}{N_A \cdot N_D} \right) \cdot V_{bi} }$ (Where $\epsilon_s$ is the permittivity of Silicon.)

Calculation yields:
W \approx 3.51 \times 10^{-5} \text{ cm}
W \approx 0.351 \text{ μm}

3. Width Distribution (Asymmetric Junction)

Since $N_D \gg N_A$, the depletion width is dominated by the lightly doped p-side ($x_p$).

• $x_n$ (n-side width): $x_n \approx 10^{-4} \cdot W \approx 0.000035 \text{ μm}$
• $x_p$ (p-side width): $x_p \approx W \approx 0.351 \text{ μm}$

AC to DC Conversion Block Diagram

The process of converting AC power to regulated DC power involves several stages:

AC $\rightarrow$ Transformer $\rightarrow$ Rectifier $\rightarrow$ Filter $\rightarrow$ Regulator $\rightarrow$ DC Load

• Transformer: Provides voltage level shifting and isolation.
• Rectifier: Converts AC input into pulsating DC (half-wave or full-wave).
• Filter (C/L/$\pi$): Reduces the ripple voltage present in the pulsating DC output.
• Regulator (Zener/Linear/SMPS): Maintains a constant DC output voltage despite changes in load current or input line voltage.

Full-Wave Bridge Rectifier Operation

• Rectifier Definition: A circuit that converts Alternating Current (AC) into Direct Current (DC).
• Bridge Rectifier (4 diodes): Uses four diodes such that two diodes conduct during each half-cycle, ensuring the load always sees the same polarity.

      ~     D1      D2
    ─~~─┬─|>|─┬─LOAD─┬─|<|─┬─~~─
        │     │      │     │
        └─|<|─┴──────┴─|>|─┘
          D3           D4

• Positive Half-Cycle: D1 & D4 conduct, current flows through the load in the positive direction.
• Negative Half-Cycle: D2 & D3 conduct, current flows through the load in the same positive direction.
• Waveforms: Input is sinusoidal; Output is full-wave rectified (all positive arches).
• Average DC Voltage (Ideal): $V_{DC} = 2V_m/\pi$. (Subtract $\sim 2V_D$ for real diode drops.)
• Ripple Factor (No Filter): $r \approx 0.482$.

Silicon Diode V-I Characteristics and Forward Current

Given a Silicon diode at $300 \text{ K}$ with Reverse Saturation Current $I_S = 800 \text{ nA} = 8.0 \times 10^{-7} \text{ A}$. Thermal voltage $V_T \approx 0.02585 \text{ V}$.

Diode Law and Forward Current Calculation

The diode current ($I$) is given by the Shockley Diode Equation:

$$I = I_S \cdot \left( e^{\frac{V_D}{n \cdot V_T}} – 1 \right)$$ (Assuming ideality factor $n \approx 2$ for a Si diode at moderate currents.)

Forward Current (Approximation, neglecting -1 term):

I(V_D) \approx 8.0\times 10^{-7} \cdot \exp\left( \frac{V_D}{2 \cdot 0.02585} \right) \text{ A}

Numeric values at common forward voltages ($n = 2$):

• $V_D = 0.55 \text{ V} \rightarrow I \approx 0.033 \text{ A}$
• $V_D = 0.60 \text{ V} \rightarrow I \approx 0.088 \text{ A}$
• $V_D = 0.65 \text{ V} \rightarrow I \approx 0.231 \text{ A}$
• $V_D = 0.70 \text{ V} \rightarrow I \approx 0.607 \text{ A}$

V–I Characteristics of a PN Junction Diode (Silicon)

• Forward Region:
  • Very small current flows until the “knee” or cut-in voltage ($\sim 0.7 \text{ V}$ for Si).
  • Beyond the knee, current rises exponentially: $I \approx I_S \cdot e^{\frac{V_D}{n \cdot V_T}}$.
• Reverse Region:
  • A small, nearly constant leakage current flows, approximately equal to $I_S$.
  • At the reverse breakdown voltage (Zener or avalanche), the current increases sharply.
• Key Points:
  • Cut-in/Threshold voltage $\approx 0.7 \text{ V}$ (Si).
  • Dynamic resistance in forward bias: $r_d = n \cdot V_T / I_F$.
  • Increasing temperature causes $V_T$ to increase slightly and $I_S$ to increase strongly, shifting the forward curve to the left.