Protection Mechanism and Segmentation in 80386 Microprocessor

Posted on Jun 4, 2024 in Computers

Protection Mechanism of 80386:

80386 protection mechanism is provided by memory management and by privilege protection.

1. Protection by Memory Management:

Memory Management uses segmentation and paging mechanism. In segmentation mechanism, the selector selects one Descriptor from the Descriptor Table and the entry of that one Descriptor provides protection parameters such as Access type, whether the descriptor is valid or invalid, limit of the segment, and its privileged level. In Access type, the data segment can be protected from write operation, the code segment can be protected from read operation, whether the segment is executable or whether it is readable/writeable can be selected. This protection is done using E, ED/C, and R/W bits. The same Access Rights are available in the Page Directory Table entry of the Paging Mechanism. The limit check depends on the G bit (Granularity Bit) which selects segments with size ranging from 1 byte to 64 KB or from 4 KB to 4 GB.

2. Privileged Protection:

  • I. Privileges are available only in Protected Mode
  • II. Four Levels of protection are provided by MMU – PL0 to PL3, required during Multitasking.
  • III. Protect User Programs, isolate user program from critical function programs to protect the system from unwanted changes.
  • IV. User programs – PL3 – Least privilege
  • V. Kernel operations – PL0 – Highest privilege
  • VI. Rules of Privilege: Data stored in a segment with privilege level P can only be accessed by a program with equal or higher privilege.

Segmentation in the 8086 Microprocessor

The 8086 microprocessor uses a segmentation memory model to divide its 1MB addressable memory space into smaller, manageable segments. This model helps in efficient memory management and better use of memory. Here’s an overview of segmentation in the 8086 microprocessor:

Segments and Segment Registers

The 8086 microprocessor divides the memory into four segments, each with a maximum size of 64KB:

  • Code Segment (CS): Contains the executable instructions of a program.
  • Data Segment (DS): Holds the data variables and constants used by a program.
  • Stack Segment (SS): Used for managing the stack, which stores temporary data like return addresses, procedure parameters, and local variables.
  • Extra Segment (ES): Additional data segment for string operations and other purposes.

Advantages of Segmentation

  • Memory Management: Segmentation allows for more efficient use of memory by enabling separate address spaces for different types of data and code.
  • Modularity: Programs can be divided into smaller, manageable modules, making them easier to understand, develop, and debug.
  • Protection: Different segments can be given different levels of protection, reducing the risk of accidental or malicious overwriting of critical memory areas.

Addressing Modes in the 8086 Processor

The 8086 microprocessor supports a variety of addressing modes, which determine how the operand of an instruction is accessed. These addressing modes provide flexibility in accessing data and instructions. Here’s a detailed overview of the addressing modes in the 8086 processor:

  • 1. Immediate Addressing Mode: In this mode, the operand is specified explicitly in the instruction itself. Example: MOV AX, 1234H (Moves the immediate value 1234H into register AX)
  • 2. Register Addressing Mode: The operand is located in a register. Example: MOV BX, AX (Moves the content of register AX into register BX)
  • 3. Direct Addressing Mode: The operand is located at a specific memory address. The address is given directly in the instruction. Example: MOV AX, [1234H] (Moves the content of memory location 1234H into register AX)
  • 4. Register Indirect Addressing Mode: The operand’s address is specified by a register pair. Example: MOV AX, [BX] (Moves the content of the memory location pointed to by register BX into register AX)
  • 5. Based Addressing Mode: The operand’s offset is given by the sum of a base register (BX or BP) and a displacement. Example: MOV AX, [BX+04H] (Moves the content of the memory location at BX+04H into register AX)
  • 6. Indexed Addressing Mode: The operand’s offset is given by the sum of an index register (SI or DI) and a displacement. Example: MOV AX, [SI+04H] (Moves the content of the memory location at SI+04H into register AX)
  • 7. Based Indexed Addressing Mode: The operand’s offset is given by the sum of a base register (BX or BP) and an index register (SI or DI). Example: MOV AX, [BX+SI] (Moves the content of the memory location at BX+SI into register AX)
  • 8. Based Indexed with Displacement Addressing Mode: The operand’s offset is given by the sum of a base register, an index register, and a displacement. Example: MOV AX, [BX+SI+04H] (Moves the content of the memory location at BX+SI+04H into register AX)
  • 9. Relative Addressing Mode: The operand is at a location specified by the current value of the Instruction Pointer (IP) plus a displacement. Example: JMP SHORT LABEL (Jumps to the label relative to the current IP)
  • 10. Inherent Addressing Mode: The operand is implied by the operation code (opcode) itself. Example: STC (Set Carry Flag – no operands are involved, the operation is inherent)

The 80386 is a 32-bit microprocessor from Intel’s x86 family. It features a flag register that stores the status of various arithmetic and logical operations. Here’s an overview of the flag register (also known as EFLAGS) in the 80386:

  • Carry Flag (CF): Set when an arithmetic operation generates a carry out of the most significant bit, or when a subtraction requires a borrow.
  • Parity Flag (PF): Set if the result of an operation contains an even number of set bits in its least significant byte.
  • Auxiliary Carry Flag (AF): Used for binary-coded decimal (BCD) arithmetic. Set when a carry or borrow occurs between the low nibble (bits 0-3) and the high nibble (bits 4-7) of an 8-bit operand.
  • Zero Flag (ZF): Set if the result of an operation is zero; otherwise, it is cleared.
  • Sign Flag (SF): Set if the result of an operation is negative (i.e., if the most significant bit is set).
  • Trap Flag (TF): Used for single-step debugging. If set, the processor generates an interrupt after executing each instruction, allowing for instruction-by-instruction debugging.
  • Interrupt Flag (IF): Controls the ability of the processor to respond to maskable hardware interrupts. If set, interrupts are enabled; if cleared, interrupts are disabled.
  • Direction Flag (DF): Affects the direction in which string instructions (e.g., MOVS, CMPS) operate. If set, string operations auto-decrement; if cleared, they auto-increment.
  • Overflow Flag (OF): Indicates signed arithmetic overflow. Set if the result of a signed operation is too large to be represented in the destination operand size (e.g., overflow in addition or underflow in subtraction).
  • Reserved Flags (RF, NT, IOPL, OF, DF, IF, TF, SF, ZF, AF, PF, CF): Reserved for future use or specific operating modes.