MIPS Datapath Control Signals and Stages Summary
Step 1:
Instruction Fetch
Fetch instruction from instruction memory, update PC to PC+4
Step 2: Instruction Decode/Register Read-Read register values and/or immediate values (Does not apply to J-type instructions)
Step 3: Execution/Memory & Target Address Calculation/Branch or Jump Completion-R/I-type: ALU operation-lw/sw: add operation (address calculation)-Branch: Condition check, target address calculation-Jump: Target address calculation
Step 4: Memory Access/R-type Instruction Completion-R/I-type:Write ALU results to Register (RD-RT)-lw/sw: read/write value from/to memory respectively
Step 5: Memory read Completionlw: write memory value to register
Step 1 – Instruction FetchPCWrite 1IorD 0MemRead 1MemWrite 0IRWrite 1PCSource 00ALUOp 00ALUSrcB 01ALUSrcA 0RegWrite 0
-PC>>Mux01,Mux02;Mux1>mem;mem>ir;4>mux13;mux2>ALU;mux3>ALU;ALUR>mux04;mux4>pc
Step 2 – Instruction Decode + Register FetchAluOp 00ALUSrcB 11ALUSrcA 0
-PC>Mux02;InstrRegister does its stuff;Read data moves into A and B ;se>sl2>mux33>ALU;ALUR>ALUOu
Step 3 – Execution : Memory ReferenceAluOp 00ALUSrcB 10ALUSrcA 1
-instr15-0>se>>mux23,sl2;A>mux12>ALU;mux3>ALU;ALU>ALUOu
Step 3 – Execution : ALU OperationALUOp 10ALUSrcB 00ALUSrcA 1
-instr15-0>ALUC;A>mux12>ALU;B>mux03>ALU;ALU>ALUOu
Step 3 – Execution : BranchALUOp 01ALUSrcB 00ALUSrcA 1PCSource 01PCWriteCond 1
-A>mux12>ALU;B>mux03>ALU;ALUZero>pcwritecond;ALU>ALUOu>mux14;mux4>PC
Step 3 – Execution : JumpPCSource 10PCWrite 1
-instr15-0>belowsl2,mux24;pc>sl2>mux24;mux4>pc
Step 4 – Memory Access : LoadMemRead 1IorD 1IRWrite 0
-mux1>add;mem>memreg;ALUOu>mux11;
Step 4 – Memory Access : StoreMemWrite 1IorD 1
-mux1>mem;B>mem;ALUOu>mux11;
Step 4 – R-type CompletionMemtoReg 0RegWrite 1RegDst 1
-instr15-0>mux15;mux5>writereg;ALUOu>mux06;mux6>writedata;
Step 5 – Memory Read CompletionRegWrite 1MemtoReg 1RegDst 0
-instr20-16>mux05>writereg;memdata>mux16>writedata;
Where do we save the control signals for different instructions in a pipelined datapath – In pipeline registers between the stages. TLB – maps virtual page number and physical page number
What is a disadvantage of a dynamic branch prediction method, like history table? – Increases hardware complexity
You are designing an internet router that will need to save it’s settings between reboots. Which type of memory should be used to save these settings? – Flash
A variable that has been accessed more than once is kept in cache. This is an example of what kind of locality? – Temporal Locality
For a Memory byte address of 420 (in decimal), given a direct mapped Cache of 2^3 1-byte blocks in total, what is the tag? Write your answer in decimal.
Index = block address mod number of sets = 420 mod 8 = 4
Block address = Byte address / block size in bytes = 420 / 1 = 420
Tag = floor(block address / number of sets) = floor(420/8) = 52
What is the length of cache block address for a 2^3 – way set associative cache with 2^0 KiB data and data per block is 2^4 Bytes.
Data = 1024 bytes | associativity = 8 | block size = 16 bytes per block
1024/16 = 64 blocks | 64/8 = 8 sets | log2(8) = 3 Block Offset: log2(words per block)Byte Offset: log2(bytes per word)Total Offset: Block + Byte OffsetIndex: log2(blocks) | Index:log2(sets)Tag: rest
Block address = byte address / bytes per block
Page size = 4kb > offset = log2 (4 * 2 ^ 10) = 12 bits
Virtual address 0x52004 > VPN = 0x52, offset = 0x004
Page table: VPN 0x52 > Valid = 1, PPN = 0x80, No page fault
Physical address = PPN + offset = 0x80 + 0x004 = 0x80004
Word at physical 0x80004 = 0x8E93000C
RegWrite 1; (R,I,Lw) 0; (sw,b,j) MemRead – 1 for lw, else 0 MemWrite – 1 for sw, else 0 ALU ControlAnd – 0000Or – 0001Add – 0010Subtract – 0110Slt – 0111NOR – 1100
ALUOpR/I – 10Lw – 00Sw – 00Beq – 01 – sub
RegDst0; I, lw1; RX; sw,b,jALUSrc0;reg val – R, b1;imm val – I, lw, swX; ALU unused, jMemtoReg0; ALU val – R, I1; mem val – lwX; no write – sw,b,j
Branch0; R, I, lw,sw, j1; bne, beqPCSrc0; PC+41; branchPcX; N/A
Jump0; non-jump1; jump