Microprocessors and Microcontrollers: A Comprehensive Guide

Microprocessors and Microcontrollers


A microprocessor is a computer’s central processing unit (CPU) on a single integrated circuit (IC). It contains the following components:

  • Arithmetic logic unit (ALU)
  • General purpose registers
  • Stack pointer
  • Program counter
  • Clock timing circuit
  • Interrupt circuit


A microcontroller is a small computer on a single IC that contains the following components:

  • Microprocessor circuitry
  • Built-in ROM
  • Built-in RAM
  • I/O devices
  • Timers
  • Counters

Comparison of Microprocessors and Microcontrollers

Number of instructionsManyFew
Bit handling instructionsFewMany
Access times for memory and I/O devicesMoreLess
Flexibility in designMoreLess
Number of multifunctioned pinsLessMore

Features of the 8051 Microcontroller

  1. 4096 bytes of on-chip program memory
  2. 128 bytes of on-chip data memory
  3. Four register banks
  4. 128 user-defined software flags
  5. 64 kilobytes each of program and external RAM addressability
  6. One microsecond instruction cycle with 12 MHz crystal
  7. 32 bidirectional I/O lines organized as four 8-bit ports (16 lines on 8031)
  8. Multiple mode, high-speed programmable serial port

Enabling and Disabling Interrupts

Certain conditions and flag settings can cause the processor to inhibit certain interrupts and exceptions at instruction boundaries. These conditions and settings are:

  1. The IF (interrupt-enable flag) controls the acceptance of external interrupts signaled via the INTR pin. When IF = 0, INTR interrupts are inhibited; when IF = 1, INTR interrupts are enabled.
  2. As with the other flag bits, the processor clears IF in response to a RESET signal. The instructions CLI (Clear Interrupt-Enable Flag) and STI (Set Interrupt-Enable Flag) alter the setting of IF. These instructions may be executed only if CPL ≤ IOPL. A protection exception occurs if they are executed when CPL > IOPL.
  3. The RF bit in EFLAGS controls the recognition of debug faults. This permits debug faults to be raised for a given instruction at most once, no matter how many times the instruction is restarted.

80386 Operating Modes

Real modeMaintains compatibility with 8086 object code. Supports the same architecture as 8086, but can access the 32-bit register set of 80386DX.
Protected modeProvides sophisticated memory management and hardware-assisted protection mechanism.
Virtual 8086 modeAllows the execution of real mode programs that are incapable of running directly in protected mode.

The Task State Segment

The task state segment (TSS) is defined by a descriptor called the TSS descriptor. It contains fields like other segments, including:

  • The B-bit in the type field indicates whether the task is busy.
  • The BASE, LIMIT, and DPL fields and the G-bit and the P-bit have functions similar to other descriptors.
  • The limit field must have a value equal to or greater than 103 (104-1), because 80386 requires a minimum of 104 bytes of storage to perform a context save.
  • To access the TSS descriptor, the procedure must have a privilege level less than or equal to (numerically) the privilege level specified by the DPL field of the TSS descriptor.

Task Switching

The 80386 performs task switching in any of four cases:

  1. A long jump or call instruction contains a selector which refers to a TSS descriptor.
  2. The selector in a long jump or call instruction refers to a task gate.
  3. The interrupt selector refers to a task gate in the interrupt descriptor table.
  4. An IRET instruction is executed with the NT bit in the EFLAGS register set.

Descriptor Privilege Level (DPL)

Descriptors contain a field called the Descriptor Privilege Level (DPL). It is the least privileged level at which a task may access that descriptor and the segment associated with that descriptor.

Current Privilege Level (CPL)

The 80386DX stores the descriptors in the internal cache (hidden portion of segment registers) for currently executing segments. Privilege levels for such descriptors are referred to as Current Privilege Level (CPL).

Requestor Privilege Level (RPL)

Selectors contain a field called the Requester’s Privilege Level (RPL). The RPL is intended to represent the privilege level of the procedure that originates a selector.

Effective Privilege Level (EPL)

When access to a new memory segment is desired, an Effective Privilege Level (EPL) is computed. This is the greater (least privileged) of CPL and RPL.

Page Translation

Page translation is the second phase of address translation. In this phase, the 80386 transforms a linear address generated by segment translation into a physical address. The page translation step is optional and is only in effect when the PG bit of CRO is set.

When paging is enabled, the paging unit arranges the physical address space into 1,048,496 pages that are each 4096 bytes long. There are three components to the paging mechanism of the 80386DX:

  • Page directory
  • Page tables
  • Page itself (page frame or page)