Microprocessor I/O Ports: Memory-Mapped vs. I/O-Mapped
Ports of Entry/Exit are two techniques for I/O. Memory-mapped I/O and I/O-mapped I/O. Microprocessors that use memory space for I/O are said to use memory-mapped I/O. Microprocessors like the 6800, 6802, 6805, 6809, and 68000 use this technique. The 8086/8088 does not use this technique; its entire memory space can be used for system memory.
I/O-mapped systems have their own address space. This architecture is known as I/O-mapped I/O. An I/O operation can be defined as follows:
- INPUT: When the microprocessor reads data from a source that is not system memory.
- OUTPUT: When the microprocessor writes data to a destination that is not system memory.
The control bus defines the type of communication. If the system uses I/O-mapped I/O, there are no separate control lines for I/O distinct from system memory.
Addressing an I/O Port: An I/O port is a unique location used to read or write data that is not system memory. Each port in the system is given a unique address, called a port selection code. During a memory operation, specific lines on the control bus are active. During an I/O operation, specific input or output read/write lines on the control bus are active.
Addresses 00F8h to 00FFh should not be used, as Intel has reserved them for future product development.
What is an I/O Device? An I/O device can be defined as hardware controlled by the system.
Input Instruction: Used to read data from an input port. Its structure is `IN accumulator`. If the port is 8 bits, data is captured in the AL register. If the port is 16 bits, data is captured in the AX register.
Output Instruction: Used to transfer data from the microprocessor to an output port. Its syntax is `OUT port, accumulator`.
Addressing via a Constant: This method uses a 1-byte instruction and a 1-byte port address. It allows access to ports located within the first 256 locations. Example: `IN AL, 03h` or `OUT 04h, AL`.
Addressing via the X Register: This method allows addressing ports located anywhere within the 65,535 allocated port locations. Example: `MOV DX, 03h` then `IN AL, DX`.
Parallel I/O Device (PIO) 8255: The 8255 is a programmable I/O device used in microcomputer systems to control peripheral hardware. It is an LSI circuit encapsulated in a 40-pin DIP. It is designed for various interface functions. The 8255 has several operating modes, defined by a control word written to the device.
The C group consists of two 4-bit ports. One 4-bit group is associated with control group A, and the other with control group B.
- Data Buffer
- Control Logic READ/WRITE
These two blocks provide the electrical interface between the microprocessor and the 8255. The 8255’s data bus buffer (DB) is connected to the microprocessor. The Control Logic READ/WRITE routes data to/from internal registers with proper synchronization.
Serial I/O Device (Universal Synchronous/Asynchronous Receiver/Transmitter, 8251A USART):
The 8251A provides two main functions:
- Transmit Mode: Serializes parallel data from the microprocessor (inserting start/stop bits for asynchronous communication) or characters for synchronization (in synchronous mode).
- Receive Mode: Converts serial data to parallel data and checks for parity errors, framing errors, and overrun errors.
This integrated circuit (IC) has a bidirectional data bus, allowing the microprocessor to program its operation via one of three control bytes. Figure 1 shows a block diagram and pin description of the USART.
The IC has separate transmitter and receiver sections, each with its own clock inputs (RXD and TXD). RXD is the serial data input (receive data), and TXD is the serial data output (transmit data). RYRDY status signals indicate that the receiver data buffer is ready to be read, and TXRDY signals indicate that the transmitter data buffer is ready to be written, respectively.