Introduction to 8085 and 8086 Microprocessors

Posted on Jun 26, 2024 in Computers

Introduction to 8085, Characteristics, Function Units, Configuration

• 8085 Microprocessor

  An 8-bit microprocessor developed by Intel in 1976. It has a 16-bit address bus, which allows it to address 64KB of memory.

• Characteristics

  Operates at 3 MHz, has 74 instructions, five 8-bit registers, and supports five hardware interrupts.

• Functional Units

  ALU for arithmetic and logical operations, registers for temporary storage, timing and control unit for instruction execution, and interrupt control for handling interrupts.

• Configuration

  Includes serial I/O lines (SID, SOD), clock generator, and control signals (RD, WR, ALE, IO/M).

Memory Mapping, Associative Mapping, Direct Mapping, Set Associative Mapping

• Memory Mapping

  The process of translating logical addresses to physical addresses.

• Associative Mapping

  A flexible method where any block of main memory can be loaded into any line of cache. It requires a tag to identify the block.

• Direct Mapping

  Maps each block of memory to a specific line of the cache. Simple but can lead to conflicts if multiple blocks map to the same line.

• Set Associative Mapping

  A compromise where blocks are mapped to any line within a certain set of cache lines. Reduces conflicts compared to direct mapping.

Microprocessor Bus Organizations, Address Bus, Control Bus, Data Bus

• Address Bus

  Unidirectional bus that carries the address to memory or I/O devices. Determines where data is read or written.

• Control Bus

  Carries control signals to manage and coordinate the various operations of the microprocessor and other components.

• Data Bus

  Bidirectional bus that transfers data between the microprocessor, memory, and peripherals. The width of the data bus determines how much data can be transferred at once (e.g., 8-bit, 16-bit).

8085 Architecture in Detail, Functional Blocks, Draw Diagram

• Functional Blocks

  ALU, register array, timing and control unit, interrupt control, serial I/O control.

• ALU

  Performs arithmetic and logical operations.

• Register Array

  Includes general-purpose registers (B, C, D, E, H, L), accumulator, program counter (PC), and stack pointer (SP).

• Timing and Control Unit

  Manages the synchronization of all operations and generates control signals.

• Diagram

  A visual representation showing the interconnections of these components (not drawable here).

Registers, General Purpose Registers, Special Purpose Registers, Flag, 16-bit, Temporary

• General Purpose Registers

  B, C, D, E, H, L used for general data manipulation.

• Special Purpose Registers

  Accumulator (A) for arithmetic and logic operations, Program Counter (PC) to point to the next instruction, Stack Pointer (SP) to manage the stack.

• Flag Register

  Contains condition flags (Sign, Zero, Auxiliary Carry, Parity, Carry) set or cleared by the ALU operations.

• 16-bit Registers

  Combinations like HL pair for addressing memory locations.

• Temporary Registers

  Internally used by the microprocessor during operations.

8085 Pins and Signals, Draw Diagram

• Pins

  Includes Vcc, GND, clock (X1, X2), reset (RESET IN, RESET OUT), interrupts (INTR, RST7.5, RST6.5, RST5.5, TRAP), serial I/O (SID, SOD), and control signals (RD, WR, IO/M, ALE, S1, S0).

• Signals

  Power supply, clock generation, control and timing, interrupt handling, serial communication.

• Diagram

  Shows the pin configuration and their functions (not drawable here).

Assembly Language Programming Basics, Instruction, Mnemonic, Assembler

• Instruction

  A binary-coded operation for the microprocessor to perform a specific task.

• Mnemonic

  A human-readable name for an instruction (e.g., MOV, ADD) that represents the binary code.

• Assembler

  A software tool that converts assembly language code (mnemonics) into machine code (binary instructions).

8085 Instruction Set, Data Transfer, Arithmetic, Logic, Branching, Machine Control

• Data Transfer

  Instructions like MOV, MVI, LDA, STA that move data between registers, memory, and I/O.

• Arithmetic

  Instructions like ADD, SUB, INR, DCR that perform arithmetic operations on data.

• Logic

  Instructions like ANA, XRA, ORA, CMP that perform logical operations.

• Branching

  Instructions like JMP, JZ, JNZ, CALL, RET that change the flow of execution.

• Machine Control

  Instructions like NOP, HLT, DI, EI that control the processor’s state and operations.

Addressing Modes, Immediate, Direct, Register, Register Indirect, Implicit

• Immediate

  Operand is specified within the instruction (e.g., MVI A, 55H).

• Direct

  Address of the operand is given in the instruction (e.g., LDA 2500H).

• Register

  Operand is in a register (e.g., MOV B, C).

• Register Indirect

  Address of the operand is in a register pair (e.g., MOV A, M where M is the memory address pointed by HL).

• Implicit

  Operand is implied by the instruction (e.g., CMA, RAR).

Memory Read and Write Cycle

• Read Cycle

  CPU places the address on the address bus, asserts the RD signal, memory places data on the data bus, CPU reads the data.

• Write Cycle

  CPU places the address on the address bus, data on the data bus, asserts the WR signal, memory writes the data from the data bus.

Instruction Cycle, Machine Cycle

• Instruction Cycle

  Comprises fetching the instruction from memory, decoding it, and executing it.

• Machine Cycle

  Subdivisions of the instruction cycle like fetch, memory read/write, I/O read/write, and execute cycles.

Types of Programming Techniques, Looping, Indexing, Counting, Delay Generation

• Looping

  Repeating a set of instructions using instructions like JMP or conditional branches (e.g., DJNZ).

• Indexing

  Accessing elements of an array or table using indexed addressing.

• Counting

  Using a counter to keep track of the number of iterations or events.

• Delay Generation

  Creating time delays using software loops to wait for a specific period.

Introduction to 8086/88 Microprocessors

The 8086/88 are 16-bit microprocessors by Intel. The 8086 has a 16-bit data bus, while the 8088 has an 8-bit data bus but internally both are 16-bit processors. They use segmented memory architecture, allowing access to 1MB of memory.

8086 Internal Architecture

The 8086 architecture consists of the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU handles instruction fetching, memory addressing, and I/O interfacing, while the EU executes instructions using the ALU and registers.

The Execution Unit, BIU, Registers

• Execution Unit (EU)

  Executes instructions, performs arithmetic and logical operations, and manipulates data in registers.

• Bus Interface Unit (BIU)

  (Details not provided in the original text)

Stack in 8085, Push, Pop, Subroutine

• Stack

  A LIFO structure in memory used for temporary storage during program execution.

• Push

  Saves register contents onto the stack (e.g., PUSH B).

• Pop

  Restores register contents from the stack (e.g., POP B).

• Subroutine

  A reusable block of code called by CALL and returned by RET instructions.

Interrupts in 8085, Hardware and Software Interrupts, Maskable Non-Maskable, Vectored

• Hardware Interrupts

  Triggered by external devices (e.g., INTR, RST7.5).

• Software Interrupts

  Triggered by software instructions (e.g., RST).

• Maskable Interrupts

  Can be enabled or disabled (e.g., RST7.5).

• Non-Maskable Interrupts

  Cannot be disabled (e.g., TRAP).

• Vectored Interrupts

  Automatically directs to a fixed memory address for the interrupt service routine.

Programmable Peripheral Devices – 8255A, 8254, 8237 Also Pin Diagram and Architecture for These

• 8255A

  Programmable Peripheral Interface with three 8-bit ports (A, B, C) that can be programmed as input or output.

• 8254

  Programmable Interval Timer with three independent 16-bit counters for timing and event counting.

• 8237

  DMA Controller that allows direct memory access without CPU intervention.

• Diagrams

  Detailed pin and architecture diagrams showing internal structure and pin configuration (not drawable here).

Register Organization in 8085

The 8085 microprocessor has a well-defined register organization that facilitates various operations and data manipulations. The primary registers in the 8085 microprocessor include:

1. Accumulator (A)

   • An 8-bit register used for arithmetic and logic operations.
   • Acts as one operand for arithmetic operations, with the result of operations stored back in the accumulator.

2. General Purpose Registers (B, C, D, E, H, L)

   • Six 8-bit general-purpose registers can be used individually or in pairs to store 16-bit data.
   • Register pairs: BC, DE, and HL.
   • HL pair is often used as a memory pointer (address register).

3. Special Purpose Registers

   • Program Counter (PC):
     • A 16-bit register that holds the address of the next instruction to be executed.
   • Stack Pointer (SP):
     • A 16-bit register that points to the top of the stack.
   • Temporary Register (W and Z):
     • Internal registers used for temporary storage during operations.
   • Instruction Register (IR):
     • Holds the opcode of the current instruction being executed.
   • Flag Register (F):
     • An 8-bit register that reflects the outcome of arithmetic and logic operations through five flags:
       • Sign (S) Flag: Set if the result is negative.
       • Zero (Z) Flag: Set if the result is zero.
       • Auxiliary Carry (AC) Flag: Set if there is a carry from the lower nibble to the upper nibble.
       • Parity (P) Flag: Set if the result has even parity.
       • Carry (CY) Flag: Set if there is a carry out of the most significant bit.

4. Instruction Decoder

   • Decodes the instructions fetched into machine language instructions that can be executed.

The combination of these registers allows the 8085 microprocessor to perform a wide range of operations efficiently.

Addressing Modes in 8085

The 8085 microprocessor supports several addressing modes, each of which specifies a different method for accessing data stored in memory or registers. These addressing modes are:

1. Immediate Addressing Mode

   • The operand is specified directly in the instruction.
   • Example: MVI A, 32H (Load the immediate value 32H into the accumulator)

2. Register Addressing Mode

   • The operand is located in a register.
   • Example: MOV A, B (Move the contents of register B into the accumulator)

3. Direct Addressing Mode

   • The operand’s address is specified directly in the instruction.
   • Example: LDA 2500H (Load the contents of memory location 2500H into the accumulator)

4. Register Indirect Addressing Mode

   • The address of the operand is specified by a register pair.
   • Example: MOV A, M (Move the contents of the memory location pointed to by the HL register pair into the accumulator)

5. Implicit Addressing Mode

   • The operand is implied by the instruction itself.
   • Example: CMA (Complement the contents of the accumulator)

6. Indexed Addressing Mode (Rarely Used in 8085)

   • Uses an index register to modify the address of the operand. This is more common in advanced microprocessors like 8086.

Internal Organization of Registers in 8086

The 8086 microprocessor has a complex register organization that includes general-purpose registers, segment registers, pointer and index registers, and status and control registers.

General Purpose Registers

1. AX (Accumulator Register)

   • Used for arithmetic, logic, and data transfer operations.
   • Can be divided into AH (high byte) and AL (low byte).

2. BX (Base Register)

   • Primarily used for base addressing.
   • Can be divided into BH and BL.

3. CX (Count Register)

   • Used as a counter in loop and string operations.
   • Can be divided into CH and CL.

4. DX (Data Register)

   • Used in I/O operations and some arithmetic operations.
   • Can be divided into DH and DL.

Segment Registers

1. CS (Code Segment Register)

   • Holds the segment address of the code segment.

2. DS (Data Segment Register)

   • Holds the segment address of the data segment.

3. SS (Stack Segment Register)

   • Holds the segment address of the stack segment.

4. ES (Extra Segment Register)

   • Holds the segment address of an extra segment for additional data storage.

Pointer and Index Registers

1. SP (Stack Pointer)

   • Points to the top of the stack.

2. BP (Base Pointer)

   • Used to access data on the stack.

3. SI (Source Index)

   • Used for string operations as the source pointer.

4. DI (Destination Index)

   • Used for string operations as the destination pointer.

Status and Control Registers

1. IP (Instruction Pointer)

   • Holds the offset address of the next instruction to be executed.

2. FLAGS (Flag Register)

   • Reflects the status of the microprocessor after arithmetic and logic operations.
   • Contains status flags (e.g., Carry, Parity, Auxiliary Carry, Zero, Sign, Overflow) and control flags (e.g., Direction, Interrupt, Trap).

The 8086 microprocessor’s register organization enables efficient data manipulation, memory access, and control of operations, making it versatile for various applications in computing.

Internal Architecture of 8254 IC

The Intel 8254 Programmable Interval Timer (PIT) is a counter/timer device designed for microprocessors to perform timing and counting functions. It has three independent 16-bit counters, each capable of handling different modes.

Internal Architecture of 8254

1. Data Bus Buffer

   • Interfaces the 8254 to the system data bus.
   • Transfers data between the microprocessor and the 8254.

2. Read/Write Logic

   • Controls the reading and writing of the counters and control words.
   • Includes control signals such as RD, WR, CS, and A0, A1.

3. Control Word Register

   • Stores the control word used to define the mode and operation of the counters.

4. Counter Registers (Counter 0, Counter 1, Counter 2)

   • Each counter has two 8-bit registers, the LSB and MSB, to form a 16-bit counter.
   • Operates in different modes based on the control word.

5. Mode Control

   • Defines the mode of operation for each counter.
   • Modes include interrupt on terminal count, hardware retriggerable one-shot, rate generator, square wave generator, software triggered strobe, and hardware triggered strobe.

6. Output Latch

   • Temporarily holds the count value for reading by the microprocessor.

7. Gate and Clock Inputs

   • Control the operation of the counters.
   • Gate: Enables or disables counting.
   • Clock: Provides the clock input for the counters.

Block Diagram

 +---------------------+
 |    Data Bus Buffer   |
 +---------------------+
        |
 +---------------------+
 |   Read/Write Logic  |
 +---------------------+
        |
 +---------------------+
 |Control Word Register|
 +---------------------+
        |
 +---------------------+    +--------+
 |   Counter 0 Register |----| Gate 0  |
 +---------------------+    +--------+
        |
 +---------------------+    +--------+
 |   Counter 1 Register |----| Gate 1  |
 +---------------------+    +--------+
        |
 +---------------------+    +--------+
 |   Counter 2 Register |----| Gate 2  |
 +---------------------+    +--------+

Bus Organization and Flag Registers in 8085

Bus Organization in 8085 Microprocessor

The 8085 microprocessor has a bus organization that includes three main types of buses:

1. Address Bus

   • The address bus is 16 bits wide, allowing the 8085 to address up to 64KB of memory.
   • It is unidirectional, carrying addresses from the microprocessor to memory or I/O devices.
   • The higher-order address bus (A15-A8) and the lower-order address/data bus (AD7-AD0) are used to specify the address of the memory location or I/O port.

2. Data Bus

   • The data bus is 8 bits wide and bidirectional.
   • It is used to transfer data between the microprocessor, memory, and I/O devices.
   • The same set of lines (AD7-AD0) are multiplexed with the lower-order address bus to carry both address and data.

3. Control Bus

   • The control bus consists of various control signals that coordinate and manage the operations of the microprocessor and peripheral devices.
   • Important control signals include:
     • RD (Read): Indicates that the microprocessor is reading data from memory or an I/O device.
     • WR (Write): Indicates that the microprocessor is writing data to memory or an I/O device.
     • ALE (Address Latch Enable): Indicates when the lower-order address/data bus is carrying address information.
     • IO/M: Distinguishes between memory and I/O operations.
     • S0 and S1: Status signals used to indicate the type of operation being performed.

Flag Registers in 8085 Microprocessor

The flag register in the 8085 microprocessor is an 8-bit register that indicates the status of the microprocessor after arithmetic and logical operations. It consists of five individual flags:

1. Sign Flag (S)

   • Set if the most significant bit (MSB) of the result is 1 (indicating a negative number in two’s complement representation).
   • Reset if the MSB is 0 (indicating a positive number).

2. Zero Flag (Z)

   • Set if the result of an operation is zero.
   • Reset if the result is non-zero.

3. Auxiliary Carry Flag (AC)

   • Set if there is a carry out from the lower nibble (bit 3) to the upper nibble (bit 4) in an 8-bit operation.
   • Used in BCD (Binary-Coded Decimal) arithmetic operations.

4. Parity Flag (P)

   • Set if the number of 1s in the result is even.
   • Reset if the number of 1s is odd.

5. Carry Flag (CY)

   • Set if there is a carry out from the most significant bit during an addition or a borrow during a subtraction.
   • Reset otherwise.

The flag register helps in making decisions based on the results of operations and is essential for branching instructions and various arithmetic and logical operations.

Mathematical and Logical Instructions in 8085

Mathematical Instructions

1. ADD (Add)

   • Instruction: ADD r
   • Operation: Adds the contents of register r to the contents of the accumulator and stores the result in the accumulator.
   • Example: ADD B

2. ADI (Add Immediate)

   • Instruction: ADI data
   • Operation: Adds an 8-bit immediate value to the contents of the accumulator.
   • Example: ADI 45H

3. SUB (Subtract)

   • Instruction: SUB r
   • Operation: Subtracts the contents of register r from the contents of the accumulator.
   • Example: SUB B

4. SUI (Subtract Immediate)

   • Instruction: SUI data
   • Operation: Subtracts an 8-bit immediate value from the contents of the accumulator.
   • Example: SUI 45H

5. INR (Increment)

   • Instruction: INR r
   • Operation: Increments the contents of register r by 1.
   • Example: INR B

6. DCR (Decrement)

   • Instruction: DCR r
   • Operation: Decrements the contents of register r by 1.
   • Example: DCR B

7. DAD (Double Add)

   • Instruction: DAD rp
   • Operation: Adds the contents of register pair rp to the contents of the HL register pair.
   • Example: DAD B (BC pair)

8. INX (Increment Register Pair)

   • Instruction: INX rp
   • Operation: Increments the contents of register pair rp by 1.
   • Example: INX B

9. DCX (Decrement Register Pair)

   • Instruction: DCX rp
   • Operation: Decrements the contents of register pair rp by 1.
   • Example: DCX B

10. CPI (Compare Immediate)

    • Instruction: CPI data
    • Operation: Compares the contents of the accumulator with an 8-bit immediate value.
    • Example: CPI 45H

Logical Instructions

1. ANA (AND)

   • Instruction: ANA r
   • Operation: Performs a bitwise AND operation between the contents of the accumulator and register r.
   • Example: ANA B

2. ANI (AND Immediate)

   • Instruction: ANI data
   • Operation: Performs a bitwise AND operation between the contents of the accumulator and an 8-bit immediate value.
   • Example: ANI 45H

3. ORA (OR)

   • Instruction: ORA r
   • Operation: Performs a bitwise OR operation between the contents of the accumulator and register r.
   • Example: ORA B

4. ORI (OR Immediate)

   • Instruction: ORI data
   • Operation: Performs a bitwise OR operation between the contents of the accumulator and an 8-bit immediate value.
   • Example: ORI 45H

5. XRA (XOR)

   • Instruction: XRA r
   • Operation: Performs a bitwise XOR operation between the contents of the accumulator and register r.
   • Example: XRA B

6. XRI (XOR Immediate)

   • Instruction: XRI data
   • Operation: Performs a bitwise XOR operation between the contents of the accumulator and an 8-bit immediate value.
   • Example: XRI 45H

7. CMA (Complement Accumulator)

   • Instruction: CMA
   • Operation: Complements (inverts) the contents of the accumulator.
   • Example: CMA

8. CMP (Compare)

   • Instruction: CMP r
   • Operation: Compares the contents of the accumulator with register r.
   • Example: CMP B

9. RLC (Rotate Left)

   • Instruction: RLC
   • Operation: Rotates the contents of the accumulator left through the carry.
   • Example: RLC

10. RRC (Rotate Right)

    • Instruction: RRC
    • Operation: Rotates the contents of the accumulator right through the carry.
    • Example: RRC

Addressing Modes in 8086

The 8086 microprocessor supports several addressing modes, which determine how the effective address of an operand is calculated. These addressing modes can be categorized into the following types:

1. Immediate Addressing Mode

   • The operand is a part of the instruction.
   • Example: MOV AX, 1234H (Move the immediate value 1234H into register AX)

2. Register Addressing Mode

   • The operand is located in a register.
   • Example: MOV AX, BX (Move the contents of register BX into register AX)

3. Direct Addressing Mode

   • The operand’s effective address is given directly in the instruction.
   • Example: MOV AX, [1234H] (Move the contents of memory location 1234H into register AX)

4. Register Indirect Addressing Mode

   • The operand’s effective address is held in a register.
   • Example: MOV AX, [BX] (Move the contents of the memory location pointed to by BX into register AX)

5. Based Addressing Mode

   • The effective address of the operand is obtained by adding a base register (BX or BP) to a displacement.
   • Example: MOV AX, [BX+1234H] (Move the contents of the memory location BX+1234H into register AX)

6. Indexed Addressing Mode

   • The effective address of the operand is obtained by adding an index register (SI or DI) to a displacement.
   • Example: MOV AX, [SI+1234H] (Move the contents of the memory location SI+1234H into register AX)

7. Based Indexed Addressing Mode

   • The effective address of the operand is obtained by adding a base register to an index register.
   • Example: MOV AX, [BX+SI] (Move the contents of the memory location BX+SI into register AX)

8. Based Indexed with Displacement Addressing Mode

   • The effective address of the operand is obtained by adding a base register, an index register, and a displacement.
   • Example: MOV AX, [BX+SI+1234H] (Move the contents of the memory location BX+SI+1234H into register AX)

9. Relative Addressing Mode

   • The effective address is determined relative to the program counter.
   • Example: JMP SHORT LABEL (Jump to a label within a range of -128 to +127 bytes from the current instruction)

These addressing modes provide flexibility in accessing data and operands, allowing for efficient and versatile instruction execution in the 8086 microprocessor.

Modes of Operation in 8255A PPI

The Intel 8255A Programmable Peripheral Interface (PPI) has three modes of operation:

1. Mode 0 (Basic Input/Output)

   • This is a simple input/output mode.
   • Ports A, B, and C can be used as simple input or output ports.
   • Each port can be individually programmed as input or output.
   • No handshaking is required, and data is simply read or written as needed.

2. Mode 1 (Strobed Input/Output)

   • This mode provides handshaking capability for input and output operations.
   • Ports A and B can be used as strobed input or output ports.
   • Each port requires the use of the corresponding handshaking lines from Port C.
   • For input operations, handshaking lines are used to signal when data is available.
   • For output operations, handshaking lines are used to signal when data has been sent and received.

3. Mode 2 (Bidirectional Bus)

   • This mode allows Port A to function as a bidirectional data bus.
   • Port A can be used for both input and output.
   • Port B and Port C are used for handshaking signals.
   • This mode is useful for transferring data between two devices in both directions.

The control word format of the 8255A is used to configure the ports in these modes. The control word is written to the control register of the 8255A to set the desired mode and direction of each port.