Flip-Flop Tables and Shift Register Configurations
Flip-Flop Characteristic Tables
The Characteristic Table summarizes the behavior of a flip-flop by listing the next state (Qn+1) for all possible combinations of the present state (Qn) and the input(s). It is derived directly from the operating rules of the flip-flop.
SR Flip-Flop Characteristics
| Present State (Qn) | Inputs (S, R) | Next State (Qn+1) | Operation |
|---|---|---|---|
| 0 | 0, 0 | 0 | Hold |
| 0 | 0, 1 | 0 | Reset |
| 0 | 1, 0 | 1 | Set |
| 0 | 1, 1 | X (Undefined) | Forbidden |
| 1 | 0, 0 | 1 | Hold |
| 1 | 0, 1 | 0 | Reset |
| 1 | 1, 0 | 1 | Set |
| 1 | 1, 1 | X (Undefined) | Forbidden |
D Flip-Flop Characteristics
| Present State (Qn) | Input (D) | Next State (Qn+1) | Operation |
|---|---|---|---|
| 0 | 0 | 0 | Reset |
| 0 | 1 | 1 | Set |
| 1 | 0 | 0 | Reset |
| 1 | 1 | 1 | Set |
JK Flip-Flop Characteristics
| Present State (Qn) | Inputs (J, K) | Next State (Qn+1) | Operation |
|---|---|---|---|
| 0 | 0, 0 | 0 | Hold |
| 0 | 0, 1 | 0 | Reset |
| 0 | 1, 0 | 1 | Set |
| 0 | 1, 1 | 1 | Toggle (0 → 1) |
| 1 | 0, 0 | 1 | Hold |
| 1 | 0, 1 | 0 | Reset |
| 1 | 1, 0 | 1 | Set |
| 1 | 1, 1 | 0 | Toggle (1 → 0) |
T Flip-Flop Characteristics
| Present State (Qn) | Input (T) | Next State (Qn+1) | Operation |
|---|---|---|---|
| 0 | 0 | 0 | Hold |
| 0 | 1 | 1 | Toggle (0 → 1) |
| 1 | 0 | 1 | Hold |
| 1 | 1 | 0 | Toggle (1 → 0) |
Flip-Flop Excitation Tables
The Excitation Table is used during the design of sequential circuits (like counters or state machines). It answers the question: “Given the present state (Qn) and the desired next state (Qn+1), what must the inputs (S, R, J, K, D, or T) be?”
For many input combinations, there may be a “Don’t Care” (X) condition, meaning the exact input value doesn’t matter, which helps simplify the final logic.
SR Flip-Flop Excitation Table
| Present State (Qn) | Next State (Qn+1) | Required Inputs (S, R) |
|---|---|---|
| 0 | 0 | 0, X |
| 0 | 1 | 1, 0 |
| 1 | 0 | 0, 1 |
| 1 | 1 | X, 0 |
Logic Behind Key Excitation Table Entries
- Qn=0 to Qn+1=1 (Set):
- SR: Must set, so S=1. R must be 0 (R=1 is forbidden).
- JK: Must set, so J=1. K can be 0 (Set) or 1 (Toggle). Thus, K=X.
- D: The next state is D’s value, so D=1.
- T: Must change state (Toggle), so T=1.
- Qn=1 to Qn+1=0 (Reset):
- SR: Must reset, so R=1. S=0.
- JK: Must reset, so K=1. J can be 0 (Reset) or 1 (Toggle). Thus, J=X.
- D: The next state is D’s value, so D=0.
- T: Must change state (Toggle), so T=1.
Do you want to see an example of how the Excitation Table is used to design a state machine, such as a synchronous 3-bit counter?
Registers and Shift Registers Fundamentals
Registers and shift registers are groups of flip-flops used to store and manipulate binary data. Registers are fundamental components in the CPU for temporary data storage, and shift registers are crucial for data movement and conversion.
A register is a collection of two or more flip-flops (usually D-type) that store a binary word of n bits. A shift register is a register designed to allow data to be moved (shifted) one position to the left or right with each clock pulse.
Shift Register Configurations
The configuration of a shift register is defined by how data is loaded into the register (input) and how it is read out (output).
| Configuration | Input Mechanism | Output Mechanism | Primary Application |
|---|---|---|---|
| SISO | Serial (1 bit at a time) | Serial (1 bit at a time) | Time delay element, simplest implementation. |
| SIPO | Serial (1 bit at a time) | Parallel (all bits simultaneously) | Serial-to-Parallel Data Conversion |
| PISO | Parallel (all bits simultaneously) | Serial (1 bit at a time) | Parallel-to-Serial Data Conversion |
| PIPO | Parallel (all bits simultaneously) | Parallel (all bits simultaneously) | Temporary storage (like a simple CPU register). |
Detailed Shift Register Types (4-bit Examples)
A. Serial-In Serial-Out (SISO)
- Structure: Flip-flops are connected in a linear cascade. The output of one flip-flop acts as the input to the next.
- Input: Data is entered one bit at a time into the first flip-flop (FF_A).
- Output: The final output is taken from the last flip-flop (FF_D).
- Operation: To shift an N-bit word through a SISO register, it takes N clock pulses to load the data, and another N clock pulses to unload the data.
- Example (4-bit): Data is available at D only after 4 clock pulses from the time it enters A.
B. Serial-In Parallel-Out (SIPO)
- Structure: Same cascaded flip-flop structure as SISO.
- Input: Data is entered serially into the first flip-flop (FF_A).
- Output: The output is taken simultaneously from the Q terminal of every flip-flop.
- Operation: It takes N clock pulses to completely load an N-bit word. Once loaded, the entire word is available immediately in parallel form.
- Application: Converting data received serially (e.g., from a communication line) into a format suitable for processing by a parallel CPU bus.
C. Parallel-In Serial-Out (PISO)
- Structure: Requires a control mechanism (usually a set of AND/OR gates or a MUX/DEMUX circuit) to switch between Load and Shift operations.
- Input (Load): All data bits are loaded simultaneously into all flip-flops using either the preset/clear inputs or dedicated parallel inputs. This is usually accomplished in one clock pulse.
- Output (Shift): After loading, the circuit is switched to shift mode. Data is then read out one bit at a time from the last flip-flop (FF_D).
- Operation: 1 clock pulse for loading, and N-1 clock pulses for shifting out the remaining bits.
- Application: Converting data from a parallel bus into a serial stream for transmission over a single line.
D. Parallel-In Parallel-Out (PIPO)
- Structure: Each input is connected directly to the D input of its corresponding flip-flop.
- Input (Load): All data bits are loaded simultaneously into all flip-flops on a single clock pulse.
- Output: The output is taken simultaneously from the Q terminal of every flip-flop.
- Operation: Both loading and retrieval are instant (one clock pulse).
- Application: Simple, fast, temporary storage register (e.g., buffer register).
Universal Shift Register
A Universal Shift Register is a sophisticated device that can perform all four shifting modes (SISO, SIPO, PISO, PIPO) as well as parallel loading and holding data, all controlled by mode select inputs. They are essential for complex data manipulation within a CPU.