Field-Effect Transistors and Op-Amp Principles

Posted on Jan 22, 2026 in Industrial Electronics and Automation Engineering

Construction and Working of an n-channel JFET

Construction

An n-channel JFET consists of a small bar of extrinsic n-type semiconductor material. Two ohmic contacts are made at its ends, serving as the drain (D) and source (S) terminals. Heavily doped p-type electrodes form reverse-biased p-n junctions on both sides of the n-type bar, creating the gate (G) terminals (usually connected together). The thin region between these two p-gates is the n-channel, through which current flows.

Working

The gate-source junction is always reverse-biased, resulting in negligible gate current (I_G ≈ 0). A positive drain-source voltage (V_DS) causes electrons (majority carriers) to flow from source to drain through the n-channel, producing drain current (I_D).

• Channel Control: The reverse bias creates depletion regions that extend into the channel, narrowing its width. Increasing the reverse gate-source voltage (V_GS, negative for n-channel) widens the depletion regions, further narrowing the channel and reducing I_D.
• Saturation: At low V_DS, I_D increases linearly (ohmic region). Beyond the pinch-off voltage (V_P), the channel narrows to a point, but I_D saturates due to carrier velocity.
• Cutoff: At V_GS = V_GS(OFF) (cutoff voltage, typically -2 to -10 V), the channel is fully depleted, and I_D = 0.
• Maximum Current: When V_GS = 0 V, I_D = I_DSS (maximum drain current).

The JFET acts as a voltage-controlled current source, with characteristics showing I_D vs. V_DS curves for different V_GS levels.

Classification of FET Types

FETs are classified into two main types based on construction and operation:

• JFET (Junction Field-Effect Transistor): Uses a p-n junction gate formed by reverse-biased p-n junctions to control the channel. It is a unipolar device; current is due to majority carriers only. Subtypes include n-channel (electrons as carriers) and p-channel (holes as carriers). It is normally on; gate voltage depletes the channel to control current.
• MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor): Uses an insulated metal gate separated by a SiO₂ dielectric; there is no physical p-n junction. Subtypes include:
  • Enhancement MOSFET: Normally off (no channel at V_GS = 0 V). Requires positive V_GS (n-channel) to induce/invert carriers and form a channel.
  • Depletion MOSFET: Normally on (pre-formed channel). Positive V_GS enhances current; negative V_GS depletes the channel.

FETs are voltage-controlled, unipolar devices with high input impedance.

Common Collector (CC) Transistor Configuration

Common Collector (CC) Configuration: Also known as an emitter follower or grounded collector. The collector is common to both input and output. The input is applied between the base and collector (ground); the output is taken between the emitter and collector (ground). It is used for buffering due to high input impedance and low output impedance.

• Biasing: Base-emitter is forward-biased; collector-emitter is reverse-biased.
• Characteristics:
  • Input: I_B vs. V_BC (similar to a diode, cut-in ~0.7 V for Si).
  • Output: I_E vs. V_EC (I_E ≈ I_C, nearly constant in the active region).
• Gains: Voltage gain ≈ 1 (follower), current gain is high (β+1), and power gain is medium.
• Application: Voltage buffer; isolates stages.

Transistor Current and Gain Calculations

First Part

In a BJT, α_dc = I_C / I_E, and I_B = I_E (1 – α_dc).

• I_E = I_B / (1 – α_dc) = 100 μA / (1 – 0.98) = 100 / 0.02 = 5000 μA = 5 mA.
• I_C = α_dc × I_E = 0.98 × 5 mA = 4.9 mA.

Explanation: Start with I_B = I_E – I_C. Substitute I_C = α I_E to get I_B = I_E (1 – α). Solve for I_E, then I_C. Verification: I_B + I_C = 0.1 + 4.9 = 5 mA = I_E.

Second Part

If I_C is measured as 1 mA and I_B is 25 μA:

• α_dc = I_C / (I_C + I_B) = 1 mA / (1 + 0.025) mA = 1 / 1.025 ≈ 0.9756.
• β_dc = I_C / I_B = 1 mA / 0.025 mA = 40.

Explanation: α_dc is the ratio of collector to total emitter current. β_dc is the collector-to-base current amplification. From measurements, compute directly.

Determining New Base Current

Using β_dc = 40 from the previous calculation, to get I_C = 5 mA:

I_B = I_C / β_dc = 5 mA / 40 = 0.125 mA = 125 μA.

Explanation: In the active region, I_C = β I_B. Solve for I_B given the target I_C. This assumes a constant β.

n-channel Enhancement MOSFET Construction

Construction

A P-type substrate with two heavily doped n+ regions (source S and drain D). A thin SiO₂ dielectric layer covers the substrate between S and D. A metal gate electrode overlays the SiO₂, forming a capacitor. There is no pre-existing channel; the substrate connects to the source internally.

Working

Normally off (V_GS = 0 V): No inversion layer; high resistance between S-D.

• Positive V_GS attracts electrons to the SiO₂-substrate interface, inverting p-type to n-type and forming an n-channel.
• When V_DS > 0 V, electrons flow from S to D through the channel (I_D increases with V_GS).
• Threshold voltage (V_TH) is required to form the channel (~1-4 V). Beyond V_TH, it operates in the linear region (low V_DS: I_D ∝ V_DS) or saturation (high V_DS: I_D constant).

Enhancement mode: The channel is “enhanced” by gate voltage.

n-channel Depletion MOSFET Construction

Construction

Lightly doped p-type substrate with heavily doped n+ source (S) and drain (D). An n-type channel is diffused between S and D. A thin SiO₂ dielectric is placed over the channel with a metal gate on top. Holes are cut in the SiO₂ for S/D contacts, and metal is deposited for terminals.

Working

Normally on (pre-formed n-channel conducts at V_GS = 0 V).

• Enhancement Mode (V_GS > 0 V): Positive gate attracts more electrons, widening the channel and increasing I_D.
• Depletion Mode (V_GS < 0 V): Negative gate repels electrons, depleting the channel, narrowing it, and reducing I_D. At pinch-off (V_GS(OFF) ≈ -2 to -6 V), I_D = 0.
• With V_DS applied, it operates in linear (low V_DS) or saturation (high V_DS) modes. It operates as a voltage-controlled variable resistor.

Comparative Analysis of Transistors

a) FET vs. BJT

FET: High Z_in, low noise; used in ICs. BJT: Amplifies current; used in discrete power applications.

b) Enhancement vs. Depletion mode MOSFET

Enhancement: Power-efficient off-state. Depletion: Analog variable resistor.

Transistor Operation as a Switch

A transistor acts as a switch in digital circuits by operating in the cutoff and saturation regions.

• Cutoff (OFF): Both junctions are reverse-biased (V_BE < 0.7 V, V_CE > saturation voltage). I_C ≈ 0, V_CE ≈ V_CC; high resistance (>MΩ), no current flow.
• Saturation (ON): Both junctions are forward-biased (I_B high, V_BE ≈ 0.7 V, V_CE ≈ 0.2 V). I_C is at maximum, low resistance (~10 Ω); full current flow.
• Switching: Low I_B leads to cutoff (open switch). High I_B leads to saturation (closed switch). Used in logic gates; fast switching via base pulse.

Transistor Operation as an Amplifier

In the active region (forward-biased BE, reverse-biased CB), a small I_B variation causes a large I_C change (I_C = β I_B).

• Biasing: Set the Q-point in the active region for linear operation.
• Amplification: The input signal modulates I_B → ΔI_C = β ΔI_B (current gain). Output across R_C gives voltage gain A_v = -β (R_C / r_e), where r_e = 26 mV / I_E (small-signal).
• Configurations: CE is used for high gain in audio/RF amps. Power gain is high due to load matching.

Module 3: Operational Amplifiers

Op-Amp Definition, Symbol, and Pin Configuration

Op-Amp: A direct-coupled, multistage, high-gain differential amplifier with high input impedance and low output impedance. Used for amplification, integration, and more.

PIN Configuration (IC 741):

• Pin 1: Offset Null
• Pin 2: Inverting Input (-)
• Pin 3: Non-Inverting Input (+)
• Pin 4: V- (-V_EE)
• Pin 5: Offset Null
• Pin 6: Output
• Pin 7: V+ (+V_CC)
• Pin 8: No Connection

Voltage Transfer Curve (VTC): Sigmoid shape. Linear region near V_i=0 (slope=A, open-loop gain ~10⁵); saturates at ±V_CC (e.g., ±13V for 741) for |V_i| > ~50 μV. Narrow linear range due to high gain; used with feedback for linearity.

Internal Block Diagram of an Op-Amp

The Op-Amp block consists of: Input Stage → Intermediate Stage → Level Shifting Stage → Output Stage.

• Input Stage: Dual-input balanced differential amp (high gain, high Z_in, low offset, high CMRR).
• Intermediate Stage: Multistage differential amp (additional gain).
• Level Shifting: Adjusts DC level to ground (avoids saturation).
• Output Stage: Push-pull class AB/B (low Z_out, high current drive, short-circuit protection).

Characteristics of an Ideal Op-Amp

• Infinite open-loop gain (A=∞).
• Infinite input impedance (R_i=∞, no input current).
• Zero output impedance (R_o=0).
• Infinite bandwidth (BW=∞).
• Infinite CMRR (rejects common signals).
• Infinite slew rate (S=∞).
• Zero PSRR (ignores supply variations).
• Zero offset voltage/current.
• Temperature-independent.

Characteristics of a Practical Op-Amp

• Open-loop gain: 2×10⁵.
• Input impedance: 2 MΩ.
• Output impedance: 75 Ω.
• Input offset voltage: 1-6 mV.
• Input bias current: 80 nA.
• Input offset current: 20 nA.
• CMRR: 90 dB.
• Bandwidth: 1 MHz (unity gain).
• Slew rate: 0.5 V/μs.
• PSRR: 30 μV/V.

Ideal vs. Practical Op-Amp Comparison

Ideal assumes perfect linearity; practical is limited by parasitics and used with feedback.

Key Op-Amp Definitions

• a) Slew Rate: Maximum dV_o/dt (V/μs); limits high-frequency response (e.g., 0.5 V/μs for 741).
• b) Differential Gain: A_d = V_o / (V+ – V-); amplifies the difference.
• c) Common Mode Gain: A_c = V_o / [(V+ + V-)/2]; unwanted common signal amplification.
• d) Common Mode Rejection Ratio: CMRR = A_d / A_c (dB); rejects common signals (90 dB typical).
• e) Open Loop Voltage Gain: A = V_o / (V+ – V-); ~10⁵ without feedback.
• f) Input Offset Voltage: V_os = minimum differential input for V_o=0 (~1 mV).
• g) Input Bias Current: I_b = (I_b+ + I_b-)/2; average base currents (~80 nA).
• h) Input Offset Current: I_io = |I_b+ – I_b-|; mismatch (~20 nA).
• i) Power Supply Rejection Ratio: PSRR = ΔV_o / ΔV_CC (μV/V); supply noise rejection (~30 μV/V).