Encoders and Flip-Flops in Digital Circuits
What is an Encoder? Designing an 8:3 Encoder
An encoder is a combinational circuit that converts an active input signal into a corresponding binary output code. It performs the opposite function of a decoder. Encoders take multiple input signals and encode them into fewer output bits. The number of output bits depends on the number of input lines.
For instance, an n-to-m encoder takes n inputs and generates an m-bit binary code as output, where m is the number of bits required to represent the number of inputs.
Types of Encoders
- 4-to-2 Encoder: Converts 4 inputs into a 2-bit output.
- 8-to-3 Encoder: Converts 8 inputs into a 3-bit output.
- 16-to-4 Encoder: Converts 16 inputs into a 4-bit output.
Design of an 8:3 Encoder
An 8-to-3 encoder has 8 input lines and 3 output lines. The encoder outputs a 3-bit binary code corresponding to the highest-numbered active input. If multiple inputs are active, the encoder outputs the binary code of the highest-priority input.
Truth Table
| Inputs (I7 – I0) | Outputs (O2 – O0) |
|---|---|
| 00000001 | 000 |
| 00000010 | 001 |
| 00000100 | 010 |
| 00001000 | 011 |
| 00010000 | 100 |
| 00100000 | 101 |
| 01000000 | 110 |
| 10000000 | 111 |
In the truth table above, I7 has the highest priority, and I0 has the lowest.
Boolean Expressions
- O2: O2 = I7 + I6 + I5 + I4 (Active if any input from I4 to I7 is active)
- O1: O1 = I7 + I6 + I3 + I2 (Active if any input from I2 to I7 is active)
- O0: O0 = I7 + I5 + I3 + I1 (Active if any input from I1 to I7 is active)
Logic Circuit Design
The 8:3 encoder uses OR gates to implement the Boolean expressions. For example, O2 is the OR of inputs I7, I6, I5, and I4.
Race Around Condition and Master-Slave Flip-Flops
Race Around Condition
The race around condition occurs in a JK flip-flop when both inputs J and K are set to 1. The output continuously toggles between 0 and 1 while the clock pulse is high, creating instability.
Eliminating Race Around with Master-Slave Flip-Flops
A master-slave flip-flop uses two JK flip-flops in series. The master responds to the clock when high, and the slave responds when low. This ensures the output updates only once per clock cycle, preventing continuous toggling.
Flip-Flops vs. Latches
| Parameter | Latch | Flip-Flop |
|---|---|---|
| Definition | Bistable, changes state based on input and clock level. | Bistable, changes state based on clock edge. |
| Clock Sensitivity | Level-sensitive. | Edge-sensitive. |
| Control | Operates while clock is active. | Operates during a specific clock edge. |
| Usage | Simple storage, timing less critical. | Synchronous systems, precise timing. |
SR Latch
An SR latch has two inputs (S, R) and two outputs (Q, Q̅). S sets Q to 1, R resets Q to 0. It maintains its state until a new input is applied.
Truth Table (NOR-based SR Latch)
| S | R | Q | Q̅ |
|---|---|---|---|
| 0 | 0 | Q | Q̅ |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | Invalid | Invalid |
SR Flip-Flop
An SR flip-flop is edge-triggered. Output changes only on a specific clock edge. S=1, R=0 sets Q to 1; S=0, R=1 resets Q to 0.
Truth Table (NAND-based SR Flip-Flop)
| Clock | S | R | Q | Q̅ |
|---|---|---|---|---|
| Rising/Falling | 0 | 0 | No Change | No Change |
| Rising/Falling | 0 | 1 | 0 | 1 |
| Rising/Falling | 1 | 0 | 1 | 0 |
| Rising/Falling | 1 | 1 | Invalid | Invalid |
Designing a JK Flip-Flop from an SR Flip-Flop
A JK flip-flop avoids the SR flip-flop’s invalid state (S=R=1) by toggling when J=K=1.
Steps
- Use an SR flip-flop as the base.
- Implement logic to control S and R based on J, K, and Q:
- S = J AND Q̅
- R = K AND Q
Truth Table (JK Flip-Flop using SR Flip-Flop)
| J | K | S | R | Q | Q̅ |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Q (previous) | Q̅ |
| 0 | 1 | 0 | Q | 0 | 1 |
| 1 | 0 | Q̅ | 0 | 1 | 0 |
| 1 | 1 | Q̅ | Q | Toggle | Toggle |