Embedded Systems: A Comprehensive Guide to Architecture, Peripherals, and IoT Frameworks

Week 1, Session 1: Embedded Systems

What is an Embedded System?

• Purpose-built system/application serving a specific purpose/application
• Minimizes cost/size/energy consumption
• Resource-constrained

Microcontroller Unit (MCU)

• Single Chip
• Processor + Memory + I/O
• Application Specific
• Low power consumption

e.g., digital thermometer, washing machine

Microprocessor Unit (MPU)

• General purpose
• Requires external components
• High computational power
• Versatile but power-consuming

e.g., laptops, servers, high-end drives

MCU vs MPU

Memory:

• MCU: Onboard RAM & Flash (e.g., Arduino, ESP32)
• MPU: External memory (Raspberry Pi, Smartphone Chips)

Power Consumption:

• MCU: Low power, battery operable
• MPU: High Power Consumption

I/O Capabilities

• MCU: Built-in I/O Capabilities (e.g., ESP32 with Wifi)
• MPU: Requires External I/O controllers (desktop with network card)

Computer Architecture

Summary of Computer Architecture

• Separation of processor & memory
• Processor fetches instructions from memory
• Registers help: program counter (PC), instruction register (IT), general-purpose registers, etc.

Buses

• Bus is a communication system that transfers data between components of a computer
• Data Buses, Address Buses

Von Neumann Architecture

– Same memory holds data & instructions

– Single set of address/data buses between processor & memory

Harvard Architecture

– Separate memories for data & instructions

– Two sets of address/data buses between processor & memory

  – Greater memory bandwidth

Instruction Set Architecture (ISA)

Reduced Instruction Set Architecture (RISC)

– Compact, uniform instructions => facilitates pipelining

– More lines of code => large memory footprint

– Allows effective compiler optimization

Complex Instruction Set Computer

– Many addressing modes & long instructions

– High code density

– Often require manual optimization of assembly code for embedded systems

ESP32 Architecture

Read Only Memory (ROM)

Traditionally considered non-volatile & “readonly” 

• Programmable read-only memory (PROM) • EEPROM (also E2PROM): electrically erasable programmable read-only memory (byte-level erase block) – Flash memory (high speed / density, but larger erase block)

I/O Peripherals

Data Transmission Modes

• Simplex Mode: In this mode, communication is unidirectional, meaning only one device can transmit data while the other can only receive. It’s the most basic form of communication & requires the least resources but doesn’t allow for feedback
• Half-duplex Mode: Devices can transmit in both directions but not simultaneously. Devices take turns transmitting, making it more efficient than simplex but less reliable than full-duplex
• Full-duplex Mode: Enables bidirectional communication where two devices can transmit & receive data simultaneously, either by using separate paths or dividing the channel’s capacity. This mode offers high reliability, especially for real-time applications, but is also more complex

Types of I/O Peripherals

Universal Asynchronous Receiver-Transmitter (UART)

• Character-oriented data link
• Asynchronous — no clock wire needed
• Need to agree on baud rate (e.g., 115200bps) & other settings (data length, STOP bits, parity bits)
• Design objective:
• Point-to-point communication between microcontrollers, sensors, etc.
• Full duplex communication
• Asynchronous serial communication • No clock line
• Components
  • Transmitter
  • Receiver
  • Baud rate generator – Baud rate: speed bits are transmitted (bits/s or bps) – Common baud rates: 4800, 9600, 19200, 57600, 115200

How does UART work?

1. 2-Wire Communication: UART requires only 2 wires for its operation – one for transmitting data (TX) & the other for receiving data (RX).

2. Asynchronous Transmission: It does not rely on a dedicated clock signal, making the transmission asynchronous. Instead, both the transmitting & receiving devices must agree on a baud rate, which determines the speed of transmission.

3. Data Packet Structure: A typical UART data packet comprises:

   • A start bit.
   • 5-9 data bits.
   • An optional parity bit for error checking.
   • 1-2 stop bits.

4. Voltage Levels: Data is transmitted bit by bit using high voltage to represent a ‘1’ & low voltage for ‘0’.

5. Error Checking: The optional parity bit can be used to check for errors in transmission by making the number of ‘1s’ in the data either even or odd. Moreover, various errors like framing, overrun, & parity errors can occur during UART communication.

In essence, UART provides a simple yet effective method for devices to communicate asynchronously over short distances.

Advantages

• Simple & widely supported
• No clock signal required (asynchronous communication)

Disadvantages

• Only support one-to-one communication
• Strict pre-communication requirements (e.g., agree on baud rate)

Real World Applications

• Serial console for configuring & debugging embedded systems
• Industrial automation, e.g., programmable logic controllers (PLC), sensors, etc.
• Wireless communication, e.g., GPS & Bluetooth module

Inter-Integrated Circuit (I2C)

Design objectives:

• Simplicity, low manufacturing cost

Features:

• 2-wire, bi-directional communication
• Master & Slave devices
• SDA: Serial Data Line for sending & receiving data. SCL: Serial Clock Line to synchronize the data transfer.

How does I2C work?

I2C (Inter-Integrated Circuit) is a synchronous serial communication protocol primarily utilized for transmitting data between devices, such as microcontrollers, sensors, & memory chips. The key aspects of I2C data transmission include:

1. Lines: I2C uses 2 bidirectional open-drain lines: Serial Data Line (SDA) & Serial Clock Line (SCL)

2. Master-Slave Model: Communication follows a master-slave model. Devices on the bus can be masters, generating the clock signal & initiating communication, or slaves, which respond when addressed

3. Start Condition: The master initiates data transfers by sending a start condition, where the SDA transitions from high to low while SCL is high

4. Address Frame: After the start condition, the master sends a 7-bit address byte with the 8th bit indicating a read or write operation. The addressed slave responds with an acknowledge (ACK) bit

5. Data Frames: For write operations, the master sends register address & data bytes. For read operations, the slave sends data bytes. Each byte is followed by an ACK bit from the recipient

6. Stop Condition: Transmission concludes with a stop condition, where the SDA transitions while the SCL is high

7. Multiple Masters & Slaves: I2C supports multiple masters & slaves on the same bus, with each slave having a unique 7-bit or 10-bit address

In the I2C protocol, the slave address can be sent twice in certain situations:

1. Initial Addressing:

   • The master first sends the slave address after the start condition to select the appropriate slave device.
   • Along with the slave address, a read/write bit is also transmitted to indicate whether the master intends to read from or write to the slave device. If this address matches any slave on the bus, the slave acknowledges by sending an ACK bit.

2. Reading from a Slave:

   • When the master wants to read data from a slave device, it initially sends the slave address with a write operation. This is done to set the slave’s internal address pointer to the specific register from which the master wishes to read.
   • Subsequently, a repeated start condition is issued, followed by transmitting the slave address again, but this time with the read bit set. This instructs the slave to transmit the data from the specified register.

In essence, the slave address is sent twice during a read operation from a specific register on the slave device. For general communication without the need for a register-specific read, the slave address is typically sent once.

Synchronous, multi-master, multi-slave, packet switched, serial comm bus

Design objectives:

• Simplicity, low manufacturing cost
• 2 wires: • SDA (Serial Data Line), SCL (Serial Clock Line) • ACK for successful transmission
• Open-drain design, pull-up resistors needed
• Applications: low-speed DAC/ADC, small OLED/LCD display, hardware configure / monitor / diagnostic, access RTC & NVRAM

Disadvantages of I2C

Limited Speed: Slower than interfaces like SPI. • Short-distance: Primarily for on-board communication. • No Inherent Error Checking: Must be added in software if needed. • Address Limitations: Potential address conflicts.

Advantages of I2C

Simple Hardware: Only 2 bus lines needed. • Flexible & Scalable: Supports multiple devices on the same bus. • Synchronous data transfer: Synchronous communication using a clock.

Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) is a synchronous serial communication interface used primarily for short-distance communication, especially in embedded systems. It operates in full duplex mode, allowing simultaneous data transmission & reception. There is no ack bit. Here’s how SPI works:

1. Master-Slave Architecture: SPI uses a master-slave relationship. One device acts as the master, generating the clock signal & controlling communication, while the other devices are slaves.

2. Clock Signal (SCK): The master device generates the clock signal, synchronizing data transmission between devices.

3. Master Output, Slave Input (MOSI) & Master Input, Slave Output (MISO): Data is transferred between the master & slave devices using these lines. The master sends data to the slave via the MOSI line, & the slave sends data to the master via the MISO line.

4. Slave Select/Chip Select (SS/CS): The master selects which slave device to communicate with using this line. Multiple slaves can have individual chip select lines or be daisy-chained.

5. Data Transmission: Data is shifted serially, with bits typically shifted out on the MOSI line & shifted in on the MISO line in a clocked sequence. Depending on the configuration, data can be transmitted on the rising or falling edge of the clock signal.

6. SPI Modes: There are 4 distinct SPI modes determined by clock polarity (CPOL) & clock phase (CPHA). These modes define the relationship between data transmission & the clock signal.

Regular SPI vs Daisy Chain Method

1. Regular SPI Mode:

• Chip Select Lines: In this mode, each SPI slave device requires a dedicated chip select (CS or SS) line from the master. As more slave devices are added, the number of chip select lines increases linearly.
• Data Transmission: Data is sent directly from the master to an individual slave based on the activated chip select line.
• Complexity: As the number of slaves increases, the number of required chip-select lines grows, potentially complicating board layout & design.

2. Daisy Chain Method:

• Chip Select Lines: All slave devices share a single chip select line, resulting in fewer required pins on the master device.
• Data Transmission: Data is propagated from one slave device to the next in the chain. The output of one slave is connected to the input of the subsequent slave. As a result, transmission time is increased since data must pass through each slave in the sequence before reaching its final destination.
• Complexity: Requires compatible clock schemes across all slaves in the chain & a protocol that supports daisy chaining. Slaves must be able to input a command & output it in the next cycle.

Advantages of CAN

Simple and low cost • Easy access • Extremely robust • Efficient

Disadvantages of CAN

1. Distance Limitation: CAN is designed to operate over distances of up to 40 meters. Vehicles or machines longer than this may face challenges
2. Software Costs: The cost of developing and maintaining software for CAN can be high, leading to increased software expenditure
3. Risk of Undesirable Interactions: There’s a possibility of undesirable interactions between nodes in the network
4. Data Collection Challenges: It can be difficult to collect and process high-volume CAN bus data from vehicles in real-time, especially in low bandwidth and varying network conditions
5. Arbitration and Synchronization: Effective synchronization of stations is essential for the arbitration technique, and the signal propagation delay must be kept under control for efficient arbitration
6. Non-Preemptive Protocol: CAN is not preemptive, which means a lower priority frame can block a higher priority one if it accessed the bus first, even though this is minimized due to small frame sizes

Pulse Width Modulation (PWM)

Pulse width modulation (PWM) is a technique utilized to control the power supplied to electrical devices by rapidly turning the power on and off. This modulation is achieved by generating a square wave signal with a variable duty cycle, which represents the proportion of time the signal is high (or on) relative to its total period

Key aspects of PWM include:

1. Duty Cycle: It indicates the percentage of time the signal remains high during one cycle. A 50% duty cycle means the signal is high and low for equal durations. If the duty cycle is above 50%, the signal remains high for the majority of the time, and vice versa
2. Frequency: Refers to the speed at which the signal switches on and off. The appropriate frequency depends on the type of load device being used

PWM operates by sending power through a large transistor that is controlled by a small signal, typically from a microcontroller. When this signal is high, the transistor permits power to flow; when low, it halts power. By swiftly toggling between these states, devices can effectively receive a fraction of the full power, even though the supply is either entirely on or off. Examples of PWM applications include controlling the brightness of LEDs and adjusting the speed of DC motors by altering the duty cycle.

PWM vs analog voltage

An analog voltage controller changes the resistors to generate specific voltage • Both can work for a DC motor • Compared with an analog voltage controller, PWM is – Higher power efficiency – Higher control precision – Rapid response times – Less complex circuits

Sensors: Transducers

Transducer: a device for which changes in one input physical domain produces corresponding changes in another output domain • Ideally, a sensor should: Sensor output Input • have a linear transfer function to the measurand • be insensitive to any other property • not influence the measured property 

In reality, the graphs are as follows:

1. Hysteresis: This is a phenomenon in which a sensor’s output depends on both its current and previous inputs due to memory effects. For instance, the output value of a sensor might depend on the direction from which an input value is approached. An example of this can be found in some tactile sensors where the output depends on both the current and past applied forces due to memory effects

2. Non-linearity: It refers to the deviation between a sensor’s actual output and the expected linear output for a given range of inputs. If a sensor exhibits non-linearity, it means that its response is not proportional over its working range. For instance, resistive force sensors (FSRs) have been identified to exhibit non-linear behaviors

3. Drift: Drift pertains to the unintended change in sensor output over time when the input remains constant. Various factors, such as changes in environmental conditions like temperature, can cause drift. Two forms of drift include:

   • Zero Drift: A change in the zero or offset reading of a sensor often caused by environmental factors, affecting the entire measurement range
   • Sensitivity Drift: It changes the slope of the sensor’s calibration curve, causing variations in the output for the same input change. This can be influenced by instabilities in the sensor’s power supply or changes in external conditions

Noise

• An unknown & unwanted deviation of a signal – Additive noise • White noise: a random signal having equal intensity at different frequencies – Additive white Gaussian noise (AWGN) – Multiplicative noise • E.g., speckle noise in radar imaging –Quantization noise

Key Metrics

Precision: how close the sampled outputs are with each other – Related to resolution

Accuracy: how close the average of sampled outputs to the actual value

Bandwidth: what frequency of input changes is detectable? Tradeoff: less-noise vs higher bandwidth (higher resolution) 

Layers of a Well-Architectured IoT Framework

1. Design and Manufacturing Layer
2. Edge Layer
3. Provisioning Layer
4. Communication Layer
5. Ingestion Layer
6. Analytics Layer
7. Application Layer