Digital Logic Circuits: Arithmetic, Data Selection, and Codes

Posted on Feb 28, 2026 in Systems Computer Engineering

Core Combinational Circuits and Digital Fundamentals

This section covers the core combinational circuits that form the backbone of digital systems. Mastery of their design, truth tables, and applications is essential for Unit III.

1. Arithmetic Circuits: Full Adder and Full Subtractor

These circuits perform the fundamental binary arithmetic operations.

A. Full Adder (FA)

A Full Adder is a combinational logic circuit that performs the addition of three single-bit binary numbers: two operands (A and B) and a carry-in (C_in) from a previous stage. It produces two outputs: Sum (S) and Carry-out (C_out).

Logic Expressions (Minimized):

• Sum (S) = A ⊕ B ⊕ C_in
• Carry-out (C_out) = A · B + C_in(A ⊕ B)

Implementation: A Full Adder can be constructed using two Half Adders and one OR gate.

B. Full Subtractor (FS)

A Full Subtractor is a combinational logic circuit that performs the subtraction of three single-bit binary numbers: the minuend (A), the subtrahend (B), and a borrow-in (B_in) from a previous stage. It produces two outputs: Difference (D) and Borrow-out (B_out).

Logic Expressions (Minimized):

• Difference (D) = A ⊕ B ⊕ B_in
• Borrow-out (B_out) = ¯A · B + ¯A · B_in + B · B_in (This can also be written as B_out = ¯AB + ¯(A ⊕ B)B_in)

Implementation: Similar to the Full Adder, a Full Subtractor can be constructed using two Half Subtractors and one OR gate.

2. Data Selectors/Distributors

A. Multiplexer (MUX) – Data Selector

A MUX is a combinational circuit that selects binary information from one of many input lines (M) and directs it to a single output line.

• Structure: It has 2ⁿ data input lines, n select lines, and 1 output line. (e.g., a 4 × 1 MUX has 4 data inputs and 2 select lines).
• Working: The n select lines determine which of the 2ⁿ input data lines is routed to the single output.
• Application (High Priority): Implementing a Boolean Function. An n-variable Boolean function can be implemented using a MUX with n-1 select lines and 2^n-1 data inputs. This simplifies circuit design by replacing gates with a single IC.

B. Demultiplexer (De-MUX) – Data Distributor

A De-MUX performs the opposite function of a MUX. It takes a single input and distributes it to one of many output lines.

• Structure: It has 1 data input, n select lines, and 2ⁿ output lines. (e.g., a 1 × 4 De-MUX has 1 data input and 2 select lines).
• Working: The single input signal is routed to the specific output line determined by the n select lines.
• Application: Data distribution, Routing data to a specific device, and Implementing Boolean Functions (as a Decoder).

3. Code Converters

A. Decoders

A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2ⁿ unique output lines.

• Function: It decodes an n-bit input code by ensuring that for any given input combination, only one output line is active (HIGH or LOW, depending on the design).
• Structure: n inputs and up to 2ⁿ outputs (e.g., a 3 × 8 decoder).
• Applications: Memory Address Decoding (selecting a specific memory chip or location), Data Demultiplexing (a decoder can be used as a De-MUX), and Implementing Boolean Functions (any n-variable function can be realized by ORing the appropriate minterms/outputs of an n × 2ⁿ decoder).

B. Encoders

An encoder performs the inverse operation of a decoder. It converts 2ⁿ (or fewer) input lines to an n-bit output code.

• Function: It encodes an input by generating a binary code corresponding to the single active input line.
• Limitation: Simple encoders (e.g., 8 × 3 Octal-to-Binary) have an issue if two inputs are active simultaneously. This is solved by the Priority Encoder, which ensures that the output corresponds to the input line with the highest designated priority, regardless of other active inputs.
• Applications: Keyboard Encoders (converting a key press into a binary or BCD code), and Data Compression.

4. Comparators: 2-Bit Magnitude Comparator

A Magnitude Comparator is a combinational circuit that compares the relative magnitudes of two binary numbers, A and B. It has three outputs: A > B, A = B, and A < B.

Design of a 2-Bit Magnitude Comparator

Let A be A₁A₀ and B be B₁B₀.

1. Equality (A=B)
   A and B are equal only if their individual bits are equal: A₁ = B₁ AND A₀ = B₀. The equality of two bits is determined by the XNOR gate (or equivalence gate): x_i = A_i ⊖ B_i = ¯(A_i ⊕ B_i).
2. Greater Than (A>B)
   The number A is greater than B if:
   
   • A₁ > B₁ (i.e., A₁=1, B₁=0) → A₁¯B₁
   • OR A₁ = B₁ AND A₀ > B₀ (i.e., A₁ ⊖ B₁ AND A₀¯B₀)
3. Less Than (A
   The number A is less than B if:
   
4. A₁ < B₁ (i.e., A₁=0, B₁=1) → ¯A₁B₁

The final circuit is built using these three minimized expressions.

Foundational Number Systems and Arithmetic

1. Number Systems & Conversions (Unit I)

You must be able to convert between the four main systems: Decimal (Base 10), Binary (Base 2), Octal (Base 8), and Hexadecimal (Base 16).

Direct Conversions (Most Efficient)

• Binary ↔ Octal: Group the binary bits in sets of three starting from the radix point (add leading/trailing zeros as needed). Each group of three corresponds to one octal digit (since 2³ = 8).
• Binary ↔ Hexadecimal: Group the binary bits in sets of four starting from the radix point. Each group of four corresponds to one hexadecimal digit (since 2⁴ = 16).

General Conversions

• Decimal to Any Base (X): Use the repeated division method by dividing the decimal number by the base X, collecting the remainders, and reading them bottom-up.
• Any Base (X) to Decimal: Use the positional weight method: Multiply each digit by its corresponding power of the base X and sum the results.
  • Example: (A₂ A₁ A₀)_X = A₂ · X² + A₁ · X¹ + A₀ · X⁰

2. Complements (Unit II)

Complements are crucial for representing negative numbers and simplifying subtraction in digital hardware using only addition circuits. 2’s Complement is the most common method.

A. 1’s Complement

The 1’s complement of a binary number is found by inverting every bit (0 becomes 1, and 1 becomes 0).

• Example: 1’s Complement of 10110₂ is 01001₂.

B. 2’s Complement (High Priority)

The 2’s complement is found by taking the 1’s complement and adding 1 to the Least Significant Bit (LSB).

• Example:
  • Binary: 10110₂
  • 1’s Complement: 01001₂
  • Add 1: 01001 + 1 = 01010₂ (2’s Complement)

Subtraction using 2’s Complement (A – B)

The subtraction operation is converted into an addition problem: A – B = A + (2’s Complement of B).

1. Find the 2’s complement of the subtrahend (B).
2. Add A to the 2’s complement of B.
3. Case 1: Positive Result (Subtrahend is smaller)
   • A Carry-out is generated. Ignore/discard the final carry.
   • The result is positive and in true binary form.
4. Case 2: Negative Result (Subtrahend is larger)
   • No Carry-out is generated.
   • The result is in 2’s complement form. To get the magnitude, take the 2’s complement of the result and attach a negative sign.

3. Codes: BCD, Gray, and Cyclic (Unit I)

A. Binary Coded Decimal (BCD)

• Concept: Each decimal digit (0-9) is represented by its 4-bit binary equivalent.
• Key Feature: The 6 combinations from 1010₂ to 1111₂ are invalid (or unused) BCD codes.
• Example: Decimal 47 is 0100 0111 in BCD (not 101111₂).

B. Gray Code (High Priority)

• Concept: It is an unweighted code where only a single bit changes between any two successive code words. This is called a unit distance code.
• Application: Essential for devices like rotary encoders to prevent errors (Glitches/Ambiguity) when multiple bits might change simultaneously during a reading.
• Conversion (Binary to Gray):
  • The MSB of the Gray code is the same as the MSB of the Binary code.
  • Each subsequent Gray bit is the Exclusive-OR (XOR) of the corresponding Binary bit and the previous Binary bit.

4. Logic Gates (Unit III)

Universal Gates: The NAND and NOR gates are “universal” because any other logic function (AND, OR, NOT, XOR, XNOR) can be implemented using only one of these two types of gates.