Computer Architecture: RISC, Pipelining, and Parallelism
RISC: Reduced Instruction Set Computer
RISC is a processor design philosophy that emphasizes simple instructions, a uniform instruction format, and faster execution using pipelining.
Key Characteristics
- Small, simple instruction set
- Fixed-length instructions
- Load/store architecture
- Most instructions execute in 1 clock cycle
- Large number of registers
- Optimized for pipelining
Examples: ARM, SPARC, MIPS, PowerPC
MIPS Architecture
MIPS (Microprocessor without Interlocked Pipeline Stages) is a specific RISC architecture developed by Stanford University, widely used for teaching and research.
Key Features
- 32-bit RISC architecture
- 32 general-purpose registers
- Simple instruction formats (R, I, J)
- No complex addressing modes
- Designed for efficient pipelining
| Basis | RISC | MIPS |
|---|---|---|
| Type | Design philosophy | Specific processor architecture |
| Instruction set | Reduced | Reduced (RISC-based) |
| Registers | Many registers | 32 registers |
| Addressing modes | Few | Very few |
| Usage | General concept | Practical implementation |
| Example | ARM, SPARC | MIPS32, MIPS64 |
Control Units
Microprogrammed Control Unit
Uses microinstructions stored in control memory to generate control signals.
- Characteristics: Control signals from microprograms, easier to modify, slower operation, requires control memory (ROM).
- Advantages: Flexible, easy debugging, simple design.
- Disadvantages: Slower than hardwired, extra memory required.
Hardwired Control Unit
Control signals are generated using fixed logic circuits (gates, flip-flops).
- Characteristics: No control memory, faster execution, complex design.
- Advantages: High speed, efficient performance.
- Disadvantages: Difficult to modify, complex implementation.
Performance Metrics
| Basis | MIPS | MFLOPS |
|---|---|---|
| Measures | Instruction rate | Floating-point operations |
| Instruction type | Any instruction | Only floating-point |
| Accuracy | Less reliable | More reliable |
| Usage | General performance | Scientific computation |
Pipeline Hazards
1. Data Hazards
Occurs when an instruction depends on the result of a previous instruction that has not yet completed.
- Types: RAW (Read After Write), WAR (Write After Read), WAW (Write After Write).
- Effects: Incorrect data used, pipeline stalls (bubbles), reduced performance.
- Solutions: Forwarding/Bypassing, pipeline stall (NOP), instruction reordering, register renaming.
2. Control Hazards (Branch Hazards)
Occurs due to branch or jump instructions when the next instruction to execute is unknown.
- Effects: Wrong instructions fetched, pipeline flush, performance loss.
- Solutions: Stalling, branch prediction (static/dynamic), delayed branching, speculative execution.
3. Structural Hazards
Occurs when hardware resources are insufficient for concurrent pipeline operations.
- Effects: Pipeline stall, reduced throughput.
- Solutions: Duplicate hardware, multi-port memory, resource scheduling.
Advanced Processor Architectures
VLIW (Very Long Instruction Word)
Executes multiple operations using a single long instruction word containing several independent instructions.
- Advantages: Simple hardware, high parallelism, low power consumption.
- Disadvantages: Large code size, complex compiler, binary compatibility issues.
Superscalar Processor
Can issue multiple instructions per clock cycle using multiple execution units.
- Advantages: High throughput, better CPU utilization, exploits ILP dynamically.
- Disadvantages: Complex hardware, dependency checking required, high power consumption.
Superpipelining
Divides pipeline stages into smaller stages, increasing pipeline depth and clock frequency.
- Advantages: Higher clock speed, better throughput.
- Disadvantages: Pipeline hazards increase, branch penalty larger.
Flynn’s Classification
- SISD: Single Instruction Single Data (Sequential execution).
- SIMD: Single Instruction Multiple Data (Data-level parallelism, e.g., GPUs).
- MISD: Multiple Instruction Single Data (Rare/theoretical).
- MIMD: Multiple Instruction Multiple Data (Most common, e.g., Multicore).
Shared Memory Architecture
A multiprocessor system where multiple processors share a single main memory through a common bus.
- Key Features: Single global memory, uniform memory access (UMA), cache coherence protocols.
- Advantages: Simple to design, easy data sharing, faster communication.
- Disadvantages: Bus contention, memory bottleneck, limited scalability.
Interconnection Networks
Omega Network
Multistage network using log₂N stages and 2×2 switching elements with perfect shuffle connections.
Baseline Network
Similar to Omega but uses a baseline permutation instead of shuffle.
Butterfly Network
Multistage network where paths resemble a butterfly structure; often used in FFT algorithms.
Crossbar Network
Fully connected switching network allowing every input to connect directly to every output.
Addressing Modes
- Register: Operand is in a CPU register.
- Register Indirect: Register contains the memory address of the operand.
- Relative: Effective address = PC + displacement.
- Immediate: Operand value is inside the instruction.
- Direct: Instruction contains the actual memory address.
Parallel Processors
- Array Processor: Multiple processing elements performing the same operation on different data (SIMD).
- Vector Processor: Operates on entire vectors using single vector instructions.
Instruction Level Parallelism (ILP)
Executing multiple instructions simultaneously by exploiting independence between instructions. Techniques include pipelining, superscalar execution, and out-of-order execution.