Computer Architecture Fundamentals: MIPS & Memory Concepts

Posted on Jun 19, 2025 in Computers

Memory Data Interpretation and Endianness

An array of 10 unsigned integers is stored in memory. Each integer occupies 3 bytes. The data, stored in little-endian format from low address to high, is:

7D21F05BE3FA665531540A6BCA73AB714750AF050A2F395F71CC0CC367AB

Problem: What is the unsigned integer in decimal read from memory if element 9 is read in big-endian format? (The first element is element 0.)

Segmentation of 3-Byte Integers

The 10 unsigned integers, each 3 bytes (6 hexadecimal digits), are segmented as follows:

1. 7D21F0
2. 5BE3FA
3. 665531
4. 540A6B
5. CA73AB
6. 714750
7. AF050A
8. 2F395F
9. 71CC0C
10. C367AB

Locating Element 9

Element 9 is C367AB.

Converting to Big-Endian Format

The data C367AB is currently in little-endian format, meaning the least significant byte (LSB) is at the lowest address and the most significant byte (MSB) is at the highest address. To convert to big-endian, we reverse the byte order:

• Little-endian: C3 (LSB) 67 AB (MSB)
• Big-endian: AB (MSB) 67 C3 (LSB)

Decimal Conversion

Converting the big-endian hexadecimal number AB67C3 to decimal:

AB67C3 (hex) = 11,233,219 (decimal)

Answer: 11233219

MIPS Instruction Encoding: The div Instruction

Instruction: div $t0, $t6

This instruction divides the value in register $t0 by the value in register $t6. The quotient is stored in the LO register and the remainder in the HI register.

MIPS R-Format Fields for div

• Opcode: For R-format instructions like div, the opcode is 0 (000000 in 6 bits).
• RS (Source Register 1): $t0 corresponds to register 8 (01000 in 5 bits).
• RT (Source Register 2): $t6 corresponds to register 14 (01110 in 5 bits).
• RD (Destination Register): The div instruction does not write to a general-purpose register directly, so this field is 0 (00000 in 5 bits).
• Shamt (Shift Amount): Not used for div, so this field is 0 (00000 in 5 bits).
• Funct (Function Code): The div function code is 0x1A (011010 in 6 bits).

Answer (in the order: opcode, funct, rs, rt, rd): 000000,011010,01000,01110,00000

MIPS Instruction Decoding: The subu Instruction

Problem: Suppose the opcode of a MIPS instruction is 0 (decimal), the funct code is 100011 (binary), and the remaining machine code is ca140 (hexadecimal), from high-order bit to low-order bit. What is the instruction? When showing the registers, use names (e.g., $t0, $s2) instead of indices (e.g., $8, $17).

Step 1: Identify the Instruction Type

The funct code 100011 corresponds to the subu (Subtract Unsigned) instruction. Since the opcode is 0, this confirms it is an R-format instruction.

Step 2: Convert Remaining Hexadecimal Code to Binary

The remaining machine code is ca140 (hexadecimal). Converting each hexadecimal character to its 4-bit binary equivalent:

• C = 1100
• A = 1010
• 1 = 0001
• 4 = 0100
• 0 = 0000

Concatenating these gives the 20-bit binary string: 11001010000101000000.

Step 3: Parse the Binary Machine Code into R-Format Fields

For R-format instructions, the fields are arranged as: opcode (6 bits) | rs (5 bits) | rt (5 bits) | rd (5 bits) | shamt (5 bits) | funct (6 bits).

Given the opcode is 000000 and funct is 100011, the 20-bit remaining code (11001010000101000000) represents rs, rt, rd, and shamt.

Step 4: Convert Register Field Values to Decimal

• rs = 11001 (binary) = 25 (decimal)
• rt = 01000 (binary) = 8 (decimal)
• rd = 01010 (binary) = 10 (decimal)

Step 5: Map Register Numbers to MIPS Register Names

Using the MIPS register conventions:

• Register 25 = $t9
• Register 8 = $t0
• Register 10 = $t2

Step 6: Construct the MIPS Instruction

The subu instruction format is subu rd, rs, rt.

Answer: subu $t2, $t9, $t0

Computer Systems Concepts: True or False Statements

Evaluate the following statements. True statements are marked with [TRUE], and false statements include a brief explanation.

1. [TRUE] The execution of programs is controlled by operating systems.
2. [TRUE] Both the data path and control units in a CPU are implemented by digital circuits which consist of gates and wires.
3. Random access storage is slower than sequential access storage. (False: Random access memory (RAM) is significantly faster than sequential access storage like tape drives.)
4. [TRUE] Theoretically, a program, no matter how large it is, can be written entirely in an assembly language.
5. [TRUE] A network card is both an input and output device.
6. On a multi-core CPU, the cores share the same ALU. (False: Each core within a multi-core CPU typically has its own Arithmetic Logic Unit (ALU).)
7. [TRUE] Modern computers can solve more complex problems with greater power efficiency and optimized memory usage compared to previous generations.
8. CPU hardware can fully detect and exploit the parallelism in software. (False: Fully detecting and exploiting software parallelism is a complex challenge, often requiring compiler optimizations or explicit parallel programming.)
9. [TRUE] Audio cards can be connected to a computer through PCI, which augments the system bus.
10. [TRUE] Multithreaded applications can spread threads across multiple cores for increased throughput.
11. [TRUE] Nowadays, computers are often considered to be in the fifth generation of electronic computers.
12. Every wafer contains multiple dies, and a single die can contain multiple cores. (False: A single die can indeed contain multiple cores, meaning not every die has only one core, and a 4-core CPU does not necessarily require 4 separate dies.)
13. Any program running on 8 CPUs at the same time can run 8 times as fast. (False: Parallel speedup is rarely linear due to factors like communication overhead, synchronization, and Amdahl’s Law.)
14. The first generation of electronic computers were built with vacuum tubes, and the next three generations of electronic computers were built with transistors. (False: Only the second generation was primarily defined by discrete transistors; subsequent generations (third and fourth) were characterized by integrated circuits and microprocessors, respectively.)