Computer Architecture: Control Units, Memory, and I/O Systems

Posted on Dec 2, 2024 in Computers

Control Unit

The control unit orchestrates operations, including reading, processing, and storing data.

Control Unit Implementations

  • Wiring Control
  • Microprogrammed Control Unit

Control Signals

  • Finite State-Machine: Control flows through states; inputs determine state transitions, activating control signals.
  • Delay-Cells: Control lines are tied to CR outputs, activating signals based on the current state.
  • Sequencer: Uses timer periods; instruction triggers specific signal activations.

Microprogrammed Control

Instructions are broken down into elementary operations, grouped into clock cycles.

Instruction Set Microprogram, Microprogram Set: Microcode.

A control ROM assigns a bit for each signal. Each implementation cycle corresponds to a ROM word with activated (1) signals. A program sequences the micro-counter. Microinstructions have control and sequencing fields.

Nanoinstructions

nxm >= n log d + dxm

Memory

Paged Virtual Memory

XXYY -> Virtual page XX, offset YY. Physical page & offset.

  1. CPU generates a virtual memory address.
  2. Searches the page table and updates the TLB.
  3. If not in the page table, a page fault occurs, and the OS loads the page into physical memory, updating the page table.
  4. Repeated access.

Substitution: Page management is handled by the OS (SW) using algorithms like LRU, FIFO, WAS.

Writing: Disk drives require post-writing location due to access restrictions.

Page Size: Affects performance, similar to cache block size.

  • Larger pages: Smaller page table (fewer pages), but impacts secondary memory efficiency.
  • Smaller pages: Less waste from internal fragmentation, less bandwidth needed for secondary memory.

Advantages: Fixed-size blocks, easier relocation, faster translation.

Segmented Virtual Memory

WWZZ -> Virtual segment WW, offset ZZ. Segment = physical address + offset.

Physical memory is divided into variable-sized blocks: segments.

Location: Segments must fit into available holes.

ID: A segment table, similar to a page table, handles translation. TLB can be used.

Substitution: Segments cannot be split (must fit).

Writing: Post-writing with location is necessary.

Advantages: Logical division, no internal fragmentation (but external fragmentation exists).

I/O

System I/O: CPU communication with the external world.

CPU Communication Port: Specifies address, communication direction (read/write), and data.

Peripheral with 3 Port Types:

  • Setting: Configuration or commands.
  • State: Peripheral status information for the CPU.
  • Data: Data to be read or written by the CPU.

Design Alternatives

Scheduled I/O

CPU controls peripherals through a program, waiting for service.

  1. CPU sends a command to the peripheral.
  2. CPU enters a wait loop while the peripheral processes the command.
  3. CPU continues with the monitoring program.

CPU is always attentive to the peripheral (waiting loops – slow). Priority-based service program (fixed).

Interrupt-Driven I/O

  1. CPU sends a command and works on other tasks until the peripheral interrupts.

Peripherals are accepted one by one in a daisy-chain, determining priority. Multiple lines require an acceptance level. After completing an instruction, the CPU checks for pending requests.

Steps: 1. Device finishes, 2. Peripheral identification, 3. Store context in CPU and registers, 4. Run ISR, 5. Continue normal operation.

Peripheral Identification:

  • Sampling or Polling: CPU program checks for interrupts.
  • Vectored Interrupts: Peripheral sends identifying data to the CPU upon interrupt. The CPU uses this to find the appropriate interrupt service routine (ISR). Vector = M[+inicio_tabla_No_vect * size].

DMA I/O

Peripheral transfers data blocks without CPU involvement, accessing memory directly.

Process: 1. CPU sets up transfer type and characteristics. 2. Peripheral prepares for transfer. 3. Peripheral transfers data to memory. 4. Peripheral notifies CPU upon completion.

DMA Controller: Manages data transfer instead of the peripheral bus, handling multiple peripherals and priorities.

I/O Processors

Dedicated CPU manages I/O exclusively. The main CPU only indicates the operation.

Device Controller

Features: CPU communication, peripheral communication, temporary data storage, timing and control, error detection.

Buses

Operating Modes (2 Phases):

Addressing Phase: Master sends address and enables control signals.

Data Phase: Write (master sends data), read (receive data), activates necessary control signals.

Control Strategy: Master element (CPU or DMA controller) initiates transfers. Multiple bus masters require arbitration.

Arbitration Types:

  • Daisy-Chain: Request and grant lines are daisy-chained through masters.
  • Separate Lines: Each master has a request line to an arbiter, which decides priority.
  • Distributed: Each master attempts to access the bus; the outcome determines the receiver.
  • Collisions: Devices access the bus directly; collisions trigger a wait-and-retry.

OS Functions: Translating logical to physical addresses, device management, I/O operation management, format conversion, error handling.