8085 Microprocessor: Flags, Memory, Pipelining, and DMA

Posted on Dec 1, 2024 in Computers

What is a Flag Register? 8085 Flags Explained

The Flag Register in the 8085 microprocessor is an 8-bit register reflecting the outcome of arithmetic and logical operations. It contains 5 main flags, each occupying one bit, indicating conditions arising during instruction execution. These flags help the microprocessor make decisions and control operations based on specific conditions.

The 8085 microprocessor has five flags:

1. Zero Flag (Z): Set when the result of an arithmetic or logical operation is zero. For example, after executing ADD A, B, if the result is zero, the zero flag is set.

2. Carry Flag (CY): Set when there is a carry or borrow during arithmetic or logical operations. For example, after executing SUB A, B, if there is a borrow, the carry flag is set.

3. Sign Flag (S): Set when the result of an arithmetic or logical operation is negative. The most significant bit (MSB) of the result determines the sign. For example, after executing SUB A, B, if the result is negative, the sign flag is set.

4. Parity Flag (P): Set when the result of an arithmetic or logical operation has an even number of 1s. For example, after executing ADD A, B, if the result has an even number of 1s, the parity flag is set.

5. Auxiliary Carry Flag (AC): Set when there is a carry or borrow between the lower nibble (bits 0-3) and the higher nibble (bits 4-7) during arithmetic or logical operations. For example, after executing ADD A, B, if there is a carry between the lower and higher nibbles, the auxiliary carry flag is set.

Main Memory vs. Control Memory

Main Memory

  • Holds the data and programs currently being executed by the CPU.
  • Contains machine-level instructions (like ADD, SUB) and data required by user programs or the operating system.
  • Directly accessed by the CPU for fetching program instructions and data. Access speed affects overall execution speed.
  • Typically volatile (RAM, like DRAM), losing data when power is off.
  • Generally slower than control memory due to larger data and code storage requirements.
  • Easily modified during program execution; programs and data can be loaded and changed.
  • Stores user programs and data.

Control Memory

  • Stores microinstructions defining the CPU’s control logic.
  • Contains microinstructions specifying the sequence of internal operations for each machine instruction (e.g., fetching operands, executing, writing back results) by generating control signals.
  • Accessed only by the CPU’s control unit, not directly by programs. Generates control signals for CPU operations.
  • Often ROM or PROM, containing fixed microinstructions for CPU operation.
  • Faster and optimized for quick access, as control signals need swift generation.
  • Usually fixed after manufacturing, defining the CPU’s basic instruction set and behavior.
  • Stores microinstructions for control.

Pipelining and its Conflicts

What is Pipelining?

Pipelining increases instruction throughput by dividing execution into multiple stages, each performing a part of the instruction. Like an assembly line, each stage processes a part of an instruction in parallel with other stages, enabling multiple instructions to be in different execution stages simultaneously, improving CPU performance.

Pipelining Conflicts

Pipelining can face issues, known as pipelining conflicts or hazards:

1. Data Hazards: Occur when instructions depend on results of previous instructions still in the pipeline. If an instruction needs data not yet computed by a prior instruction, it causes a delay.

2. Control Hazards: Happen when the pipeline makes assumptions about instruction flow interrupted by control instructions (like branches). A branch instruction in the pipeline may alter the flow of upcoming instructions, leading to incorrect or wasted instruction fetches.

3. Structural Hazards: Arise when hardware resources are insufficient to support all pipeline stages simultaneously. If two stages need the same memory unit at the same time, a structural hazard occurs, resulting in a stall or delay.

Direct Memory Access (DMA)

Direct Memory Access (DMA) allows hardware subsystems to access main system memory (RAM) independently of the CPU, improving data transfer efficiency, especially for large data amounts (audio/video streaming, hard drive operations, peripheral communication).

Key Aspects of DMA

1. Purpose and Functionality: DMA enables devices (disk drives, graphics cards, network adapters) to transfer data directly to/from memory without CPU involvement for each byte.

2. DMA Controller: A specialized hardware unit manages data transfer between devices and memory.

3. Modes of DMA:

  • Burst Mode: Transfers large data chunks in bursts; the CPU is temporarily halted.
  • Cycle Stealing Mode: DMA controller takes bus control during a small part of the CPU’s cycle, allowing CPU processing to continue.
  • Transparent Mode: DMA controller transfers data only when the CPU is not using the bus, making it less intrusive but slower.

4. Benefits:

  • Improved Performance: Offloading data transfer allows the CPU to focus on critical processing tasks, improving system efficiency.
  • Reduced CPU Load: Minimizes CPU involvement in repetitive data movement, lowering power consumption and freeing resources.
  • High Data Transfer Rates: Essential for fast data handling (gaming, streaming, real-time data processing).

Instruction Cycle in 8085

The instruction cycle in the 8085 microprocessor is the sequence of operations the CPU performs to fetch, decode, and execute an instruction from memory:

1. Fetch Cycle: The microprocessor fetches the instruction from memory. The program counter (PC) provides the address, placed on the address bus. The instruction is retrieved and stored in the instruction register.

2. Decode Cycle: The fetched instruction is interpreted. The instruction decoder determines the operation type and operands required.

3. Execute Cycle: The microprocessor performs the operation specified by the instruction (arithmetic/logical operations, data movement, control instructions).

4. Memory Access (if needed): Some instructions require additional memory access to read or write data.

Hardwired vs. Microprogrammed Control Units

Hardwired Control Unit

  • Generates control signals using logic circuits.
  • Faster due to hardware-generated control signals.
  • Difficult to modify as control signals are hardwired.
  • More expensive due to logic gate realization.
  • Cannot handle complex instructions easily.
  • Limited number of instructions due to hardware implementation.
  • Used in Reduced Instruction Set Computers (RISC).

Microprogrammed Control Unit

  • Generates control signals using microinstructions stored in control memory.
  • Slower as microinstructions generate signals.
  • Easy to modify at the instruction level.
  • Less expensive as only microinstructions are used.
  • Can handle complex instructions.
  • Can generate control signals for many instructions.
  • Used in Complex Instruction Set Computers (CISC).