8085 Microprocessor Architecture & Assembly Language Fundamentals

Posted on Sep 20, 2025 in Mathematics and Computer Science

Bus Organization in 8085 Microprocessors

A bus in the 8085 microprocessor is a group of wires used for communication between different components. There are three main types:

Data Bus: Carries actual data, like a delivery van.
Address Bus: Carries the memory address to access data, like a GPS.
Control Bus: Carries control signals (e.g., read/write instructions). These signals coordinate data movement between the CPU, memory, and I/O devices.

Memory Addressing & Mapping Fundamentals

Memory addressing refers to assigning unique addresses to each memory location. Memory mapping refers to the process of assigning these memory addresses to peripheral devices. There are two main types:

Memory-mapped I/O: Shares the CPU’s address space with memory, allowing regular memory instructions for I/O interaction.
Isolated (I/O-mapped) I/O: Uses dedicated IN/OUT instructions for a separate I/O address space.

8085 General Purpose Registers

The 8085 microprocessor features general-purpose registers such as B, C, D, E, H, and L, used for storing temporary 8-bit data. The H and L registers can be combined to form a 16-bit register pair (HL) for addressing. These registers act like scratchpads for the CPU, facilitating quick calculations and data movement.

8085 Special Purpose Registers

The 8085 includes several special-purpose registers:

Accumulator (A): Central to all arithmetic and logic operations.
Program Counter (PC): Tracks the sequence of instructions.
Stack Pointer (SP): Manages the top of the stack.
Flag Register: Indicates the status of operation results (e.g., zero, carry, sign).

8085 Microprocessor Pins and Signals

The 8085 microprocessor is a 40-pin Integrated Circuit (IC). Its pins are categorized into:

Address/Data Lines: (AD0–AD7, A8–A15) for memory and I/O addressing and data transfer.
Control Lines: (RD̅, WR̅, IO/M̅) for managing read/write operations and distinguishing between memory and I/O.
Power Supply: (Vcc, GND) for providing electrical power.
Interrupt Lines: (INTR, RST 5.5, RST 6.5, RST 7.5, TRAP) for responding to external events.

Basics of 8085 Assembly Language

Assembly language employs mnemonics (e.g., MOV, ADD, SUB) to represent machine instructions. Each mnemonic is translated into its corresponding machine language (opcodes) by an assembler. This low-level language allows direct communication with the CPU using concise commands, where each instruction typically consists of an opcode and its operands.

Opcode and Mnemonics Explained

A mnemonic is a human-readable instruction (e.g., MOV, ADD) that represents an operation. An opcode is the machine-readable binary code equivalent (e.g., MOV A, B translates to 78H). Mnemonics are for programmers, while opcodes are directly understood by the CPU.

8085 Instruction Set Categories

The 8085 instruction set is broadly categorized into five groups:

Data Transfer: Instructions like MOV A, B (move data).
Arithmetic: Instructions like ADD B (perform addition).
Logical: Instructions like ANA A (perform logical AND).
Branching: Instructions like JZ label (change program flow).
Control: Instructions like HLT (halt processor).

8085 Data Transfer Instructions

These instructions (e.g., MOV, MVI, LDA, STA) facilitate the movement of data between registers, memory, and I/O ports. They copy data without performing any processing.

8085 Arithmetic and Logic Instructions

This group includes instructions for arithmetic operations (e.g., ADD, SUB, INR, DCR) and logical operations (e.g., ANA, XRA, CMP). They perform mathematical or logical computations and update the Flag Register based on the results.

8085 Addressing Modes Explained

Addressing modes define the ways the CPU accesses data or operands. The 8085 supports several modes:

Immediate: The operand is part of the instruction itself (e.g., MVI A, 05H).
Register: The operand is in a CPU register (e.g., MOV A, B).
Direct: The instruction specifies the exact 16-bit memory address of the operand (e.g., LDA 2050H).
Register Indirect: The instruction specifies a register pair (HL) that holds the 16-bit memory address of the operand (e.g., MOV A, M where M = memory[HL]).
Implied: The operand is implicitly defined by the instruction itself (e.g., CMA for Complement Accumulator).

8085 Timing and Execution Cycles

An instruction’s execution involves multiple machine cycles, with each machine cycle comprising several T-states. A T-state represents one clock pulse. Common machine cycles include Opcode Fetch, Memory Read, Memory Write, I/O Read, and I/O Write.

Understanding 8085 Machine Cycles

A machine cycle is a fundamental operation performed by the CPU, such as fetching an opcode, reading data from memory, or writing data to memory/I/O. Each machine cycle is composed of a specific number of T-states. For instance, an Opcode Fetch typically requires 4 to 6 T-states.

Types of I/O Addressing in Microprocessors

There are two primary methods for the CPU to communicate with I/O devices:

Memory-mapped I/O: In this scheme, I/O devices share the same address space as memory. The CPU uses standard memory access instructions (e.g., LDA, STA) to interact with I/O ports.
Isolated (I/O-mapped) I/O: Here, I/O devices have a separate address space from memory. The CPU uses dedicated I/O instructions (e.g., IN, OUT) to communicate with I/O ports.

8085 Assembly Programming Techniques

Effective 8085 assembly programming often utilizes several techniques:

Looping: Repeating tasks using instructions like DCR (decrement) and JNZ (jump if not zero).
Conditional Execution: Executing code blocks based on conditions using instructions like CMP (compare), JC (jump if carry), and JZ (jump if zero).
Delays: Creating time delays using empty loops.
Subroutines: Implementing reusable blocks of code with CALL and RET instructions.
Block Transfer: Copying a block of memory data using a loop.

Stack Operations and Subroutines in 8085

The stack is a temporary storage area in memory that operates on a Last-In, First-Out (LIFO) principle, managed by instructions like PUSH, POP, CALL, and RET. Subroutines are reusable blocks of code that can be called from different parts of a program. The CPU utilizes the stack to store the return address when a subroutine is called, ensuring proper program flow.

Detailed 8085 Stack Operations

Key stack operations include:

PUSH: Stores the content of a register pair onto the stack.
POP: Retrieves data from the top of the stack into a register pair.
CALL: Jumps to a subroutine and saves the return address on the stack.
RET: Returns from a subroutine by retrieving the saved address from the stack.

Stack-Microprocessor Data Transfer

Data is transferred between the microprocessor’s registers and the stack using PUSH (register to stack) and POP (stack to register) instructions. Similarly, CALL instructions push the return address onto the stack, and RET retrieves it. The Stack Pointer (SP) automatically decrements by 2 for each PUSH/CALL operation and increments by 2 for each POP/RET operation.

8085 Interrupt System and Handling

An interrupt is a signal that temporarily pauses the main program execution to handle an urgent task or event. The 8085 microprocessor supports several interrupt types:

TRAP: A non-maskable interrupt, highest priority.
RST 7.5, RST 6.5, RST 5.5: Maskable, vectored interrupts with decreasing priority.
INTR: A general-purpose maskable interrupt, lowest priority.

The EI (Enable Interrupts) and DI (Disable Interrupts) instructions control the CPU’s response to maskable interrupts.

Developing Interrupt-Driven Programs

In an interrupt-driven program, the CPU executes its main loop while awaiting an interrupt signal. Upon receiving an interrupt, the CPU saves its current state and jumps to an Interrupt Service Routine (ISR). After the ISR completes and executes a RET instruction, the CPU restores its state and resumes the main program. This method is more efficient than continuous polling for events.

Microprocessor Peripheral Interfacing

Peripheral interfacing involves connecting external devices (e.g., LEDs, sensors, keyboards) to the CPU through I/O ports. This connection can be achieved using either memory-mapped or isolated I/O techniques. Dedicated interface chips, such as the 8255, 8253, and 8259, are often employed to manage these connections efficiently.

Common Programmable Peripheral Devices

Several programmable peripheral interface controllers are commonly used:

8255: Programmable Peripheral Interface (PPI) for general-purpose I/O ports.
8253/8254: Programmable Interval Timer (PIT) for generating delays and timing events.
8259: Programmable Interrupt Controller (PIC) for managing multiple interrupt requests.
8279: Keyboard/Display Controller for interfacing with keyboards and displays.
8251: Universal Synchronous/Asynchronous Receiver/Transmitter (USART) for serial communication.

Introduction to 8086/8088 Microprocessors

The 8086 and 8088 are 16-bit microprocessors featuring 20-bit address lines, enabling access to 1MB of memory. The 8086 has a 16-bit data bus and a 6-byte instruction queue, while the 8088 uses an 8-bit data bus and a 4-byte queue. Both support pipelining and segmented memory architecture using segment registers (CS, DS, SS, ES).

8086 Addressing Modes Overview

The 8086 offers a flexible set of addressing modes:

Immediate: Operand is part of the instruction (e.g., MOV AX, 1234H).
Register: Operand is in a general-purpose register (e.g., MOV AX, BX).
Direct: Operand’s effective address is specified directly in the instruction (e.g., MOV AX, [1234H]).
Register Indirect: Operand’s effective address is in a base or index register (e.g., MOV AX, [BX]).
Based + Indexed: Effective address is the sum of a base register and an index register (e.g., MOV AX, [BX+SI]).
With Displacement: Effective address includes a base/index register and a constant displacement (e.g., MOV AX, [BX+SI+05H]).

8086 Registers and Flag Register

The 8086 microprocessor includes:

General-purpose Registers: AX, BX, CX, DX (each 16-bit, can be accessed as 8-bit halves).
Segment Registers: CS (Code Segment), DS (Data Segment), SS (Stack Segment), ES (Extra Segment) for memory segmentation.
Pointer/Index Registers: SP (Stack Pointer), BP (Base Pointer), SI (Source Index), DI (Destination Index) for addressing within segments.

The Flags Register indicates the status of operations, including ZF (Zero Flag), CF (Carry Flag), SF (Sign Flag), OF (Overflow Flag), and others.